Abstract: A nonlinear equalizer for iteratively equalizing a data communication channel, which comprises a transmitter at the input of the channel, for transmitting data and one or more training sequences over the channel; a receiver at the output of the channel, for receiving the data and the one or more training sequences; a sampling circuit for sampling received data; a processor, for processing the samples. The processor is adapted to calculate the derivative of the MSE for each of the FFE taps; calculate the derivative of the variance of the enhanced noise with the FFE taps; iteratively update the FFE coefficients, while during each update, injecting samples of a known training sequence into the channel.

Abstract: Method and system for providing seamless match point switching in an adaptive decoder (e.g., an MLSE decoder) that is based on estimation of symbol sequences, according to which statistics regarding samples corresponding to different symbol sequences in alternative match points are collected by a statistics collector, to create a set of figures of merit representing the quality of each alternative match point, while different match points are obtained by changing the delay of symbols decoded by the adaptive decoder and samples entering the statistics collector. A figure of merit of the current match point is compared to the figure of merit of alternative match points. Whenever an alternative match point figure of merit is better than the current match point by a predefined threshold, a decision to switch to the alternative match point is made.

Abstract: A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.

Abstract: Method and system for estimating an eye diagram display of a real signal passing through a data communication channel, according to which decoded symbols of the transmitted real signal are captured, along with their corresponding ADC sample values and sampled at a rate of 1 SPS or more. Then statistic data is collected for each captured sequence of bits/symbols for each particular phase and a synthetic signal is created, based on the collected statistics, using a signal generator that produces samples by randomly creating a bit stream by generating a corresponding one or more samples for any symbol sequences in the bit stream according to the number of collected phases. Interpolation on the corresponding samples is then performed, according to required display time resolution and the synthetic signal is then displayed as a two-dimensional eye diagram image, representing all the statistics collected at all phases.

Abstract: An optical communication system with nonlinear equalization capability for equalizing distortions of a data communication channel, which comprises a processor for periodically gathering a predetermined number of consecutive data segments from an input data stream to a group and adding a known pilot sequence to the group, thereby forming a data frame; an optical transmitter at the input of the channel, for transmitting the data frames to a receiver, over the channel; a receiver at the output of the channel, for detecting the transmitted frames, the receiver including a demodulator.

Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.

Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.

Abstract: System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.

Abstract: A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers.

Abstract: A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of

Abstract: A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.

Abstract: An optical modulator with a region with non-linear characteristics with optimized BER performance, which comprises circuitry for adjusting the spacing between power levels of optical signals at the output of the optical modulator by adjusting the bias point of the optical modulator to be closer to a nonlinear region of the modulator, such that modulating signals having lower power will be compressed by the nonlinear region more than modulating signals having higher power. During adjustment, larger spacing between higher power levels of optical signals is introduced at the output of the optical modulator and lower spacing between lower power levels of optical signals is introduced at the output of the optical modulator.

Abstract: System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

Abstract: An electro-optical FIR transmit filter comprising a segmented MZM including a plurality of MZM segments, for receiving an input optical traveling wave to be filtered; an electrical field driver, for applying a controlled electrical field required for modulation of each MZM using a control signal which controls the electrical field; delay cells associated with at least one MZM, for aligning the control signal with a travelling optical wave; and at least one electrical xT delay cell representing a filter delay, for electrically adjusting the timing of the control signal. The FIR filter's coefficients are implemented in the optical domain by determining the amount of MZM segments driven by each xT delay cell, with respect to the total number of MZM segments.

Abstract: Method and system for providing seamless match point switching in an adaptive decoder (e.g., an MLSE decoder) that is based on estimation of symbol sequences, according to which statistics regarding samples corresponding to different symbol sequences in alternative match points are collected by a statistics collector, to create a set of figures of merit representing the quality of each alternative match point, while different match points are obtained by changing the delay of symbols decoded by the adaptive decoder and samples entering the statistics collector. A figure of merit of the current match point is compared to the figure of merit of alternative match points. Whenever an alternative match point figure of merit is better than the current match point by a predefined threshold, a decision to switch to the alternative match point is made.

Abstract: Method and system for estimating an eye diagram display of a real signal passing through a data communication channel, according to which decoded symbols of the transmitted real signal are captured, along with their corresponding ADC sample values and sampled at a rate of 1 SPS or more. Then statistic data is collected for each captured sequence of bits/symbols for each particular phase and a synthetic signal is created, based on the collected statistics, using a signal generator that produces samples by randomly creating a bit stream by generating a corresponding one or more samples for any symbol sequences in the bit stream according to the number of collected phases. Interpolation on the corresponding samples is then performed, according to required display time resolution and the synthetic signal is then displayed as a two-dimensional eye diagram image, representing all the statistics collected at all phases.

Abstract: An optical communication system with nonlinear equalization capability for equalizing distortions of a data communication channel, which comprises a processor for periodically gathering a predetermined number of consecutive data segments from an input data stream to a group and adding a known pilot sequence to the group, thereby forming a data frame; an optical transmitter at the input of the channel, for transmitting the data frames to a receiver, over the channel; a receiver at the output of the channel, for detecting the transmitted frames, the receiver including a demodulator.

Abstract: A nonlinear equalizer for iteratively equalizing a data communication channel, which comprises a transmitter at the input of the channel, for transmitting data and one or more training sequences over the channel; a receiver at the output of the channel, for receiving the data and the one or more training sequences; a sampling circuit for sampling received data; a processor, for processing the samples. The processor is adapted to calculate the derivative of the MSE for each of the FFE taps; calculate the derivative of the variance of the enhanced noise with the FFE taps; iteratively update the FFE coefficients, while during each update, injecting samples of a known training sequence into the channel.

Abstract: A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of