Abstract: An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for providing fast searches and while reducing address table size used in the processing of communication system (e.g., Internet Protocol (IP), layer-3 switches and ATM switches using E.164 addressing) addresses for identifying the source and destination of each digital packet data.

Abstract: An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for providing fast searches and while reducing address table size used in the processing of communication system (e.g., Internet Protocol (IP), layer-3 switches and ATM switches using E.164 addressing) addresses for identifying the source and destination of each digital packet data.

Abstract: A method is described of programming a memory array on a single integrated circuit so that a portion of each data word is characterized as CAM, with the remaining portion of each data word functioning as RAM. The programmable memory array is partitioned into CAM and RAM subfields by disabling the comparators in each memory cell in selected columns of CAM cells to create RAM-functioning cells. Said partitioning may be re-programmed to enable the comparators in said RAM-functioning cells to be re-enabled, so that said cells may participate in subsequent comparisons to a search word. The described memory array permits direct retrieval and storage of associated information in RAM-functioning cells corresponding to data words which are determined to match a given search word. This direct retrieval and storage process can efficiently be utilized without computing or decoding an address for the associated information.