Abstract: A system and method in which a warm-reset request event is detected by reset hardware that subsequently blocks the warm reset request and places the SDRAM in a self-refresh mode in which the SDRAM data continually refreshes its stored data. Once the SDRAM is in the self-refresh mode the reset hardware resets the SDRAM's controller. Because the SDRAM is in the self-refresh mode when its controller is reset, none of the invalid signals on the controllers control lines will affect the stored data.

Abstract: The present invention pertains to an apparatus and method for automatically configuring disk drives connected to a RAID controller. The automatic configuration mechanism is able to generate a full configuration of the disk drives connected to a RAID controller both at system initialization or bootup and at runtime. The mechanism uses a robust criteria to configure the disk drives which allows the drives to be configured in accordance with one or more RAID levels and which considers any existing configurations. The automatic configuration mechanism is advantageous since it eliminates user interaction, time, and knowledge often required to configure disk drives connected to a RAID controller.

Abstract: The present invention pertains to an apparatus and method for transparently coupling PCI devices behind a PCI-to-PCI bridge. A controller is coupled to a primary PCI bus and includes a secondary PCI bus that is coupled to the primary PCI bus by a PCI-to-PCI bridge. The secondary PCI bus includes a number of exposed PCI devices that are recognizable by the bridge and a number of hidden PCI devices that are hidden from the bridge. A bridge assist device (BASS) is one such exposed PCI device that is used to acquire a memory address space that is part of the system memory. The memory address space is then partitioned by the controller and assigned to each of the hidden PCI devices. The hidden PCI devices use the memory address space to transmit data to the local CPU. The controller also includes a local-to-PCI bridge that is coupled to the secondary PCI bus and a local bus including a memory and a processor.

Abstract: A reset circuit implemented in a RAID controller configured for dual active operation. The reset circuit generates a reset pulse with a relatively invariant pulse width that is coupled to the controller's main CPU and I/O processors. The reset pulse can be generated in response to activation of an external common reset signal. The external common reset signal is activated by an external system (e.g., another controller configured for dual active operation) whenever the controller needs to be reset. This can be when the controller fails to maintain a communication signal transmitted to the external system or when the external system has inconsistent configuration information, requiring the entire system (i.e., both the controller and the external system) to be re-initialized. The reset pulse can also be generated in response to internal reset instructions issued by the controller's main CPU.

Abstract: A reliable event delivery system for use in a distributed event driven system in which one or more servers are each connected by a reliable communication transport system to a client station. Each server communicates event messages over a reliable transport system to the client station for execution. Receipt of the event messages at the client station transport protocol level is guaranteed by the reliable transport system. Guaranteed delivery at the client station's event execution level is achieved by the client station providing an event execution acknowledgment to the server. Another embodiment provides for secure and reliable event delivery by using a second transport system for use by the client station for requesting a confirmation from a server that an event message received over the first transport system was sent from the server and intended for the client.

Abstract: A RAID (3, 4, or 5) disk array memory system incorporates a method and apparatus for the management of faulty data that eliminates the unintentional creation of spurious data when a double fault occurs. For example, when a disk drive failure occurs in one channel and the failed disk is replaced, reconstruction of the data can be achieved because a parity drive channel is provided for correcting errors. If a read error occurs during reconstruction of the failed disk data, the block corresponding to the error block does not allow the reconstruction of the corresponding failed disk block. To prevent the misuse of the two data blocks, a bad data table (BDT) is constructed that lists the addresses of the block just read and the block to be reconstructed. Also a standard filler block is written into the two bad blocks and a new parity block is created. The addresses of all access requests to the memory array are compared with the BDT and, if not listed, the access proceeds.

Abstract: A method and apparatus for dynamically expanding an N drive RAID set to an M drive RAID set while maintaining data integrity, where the M drive RAID set includes one or more new drives. The method comprises the steps of identifying a destructive zone in the N drive RAID set including destructive zone data. Thereafter the destructive zone data is mirrored in the M drive RAID set by copying it to a free location in the N drive RAID set and to a location in a new drive in the M drive RAID set. Finally, the N drive RAID set is expanded to an M drive RAID set. Data integrity is assured in the N drive RAID set during migration by maintaining mirrored destructive zone data until the expansion step has completed migration of the destructive zone of the N drive RAID set.

Abstract: A battery backup mirrored cache memory module for a cache dynamic random access memory (DRAM) system that senses the V.sup.cc level supplied through the cache controller to the cache memory and, if the cache controller supplied V.sup.cc falls below a preset threshold level, the battery backup apparatus switches the cache memory array to a backup battery V.sup.cc source, and a backup refresh control generator unit that is also powered by the backup battery V.sup.cc source. The cache DRAM, backup battery, and backup refresh generator are physically contained in a single module that can be disconnected from the cache controller and host computer system while preserving cache memory contents. The backup system is installed in an operating host system for recovery of the cache memory contents and/or resumption of execution of the program that was running when the V.sup.cc power failure occurred.

Abstract: A method and apparatus providing a battery backup for a dynamic random access memory (DRAM) cache system that senses the V.sub.cc level supplied through the cache controller to the cache memory and, if V.sub.cc falls below a preset threshold level, the battery backup apparatus switches the cache memory array to a backup battery V.sub.cc source, and a backup refresh control generator unit that is also powered by the backup battery V.sub.cc source. The cache DRAM, backup battery, and backup refresh generator are physically contained in a single module that can be disconnected from the cache controller and host computer system while preserving the cache memory contents. The backup system is installed in an operating host system for recovery of the cache memory contents and/or resumption of execution of the program that was running when the V.sub.cc power failure occurred.

Abstract: For controlling the acquisition of data in an optical character recognition system having a head for scanning characters, a guide is provided to be disposed along the series of characters. A rail on the guide cooperates with a groove in the head to guide the head along the characters. Disposed on the guide is a reticle having a saw-toothed pattern with segments at 45.degree. with respect to the rail. A linear sensor array, attached to the head normal to the groove monitors the position of points of the reticle normal to the track. This normal position is then translated to the position of the head. Every time the head moves a predetermined distance, it is caused to output data relating to the series of characters. The invention can also be employed to monitor position in any system having an element that moves along a path.