Abstract: An apparatus and method for rotating OSD fonts are disclosed. The OSD rotation device including a central processing unit, font addresses generator, memory, a font ROM, a decoder, a shift register, a output controller and output circuits, a synchronization signal generator, and a display device. In a manner, the OSD fonts corresponding to the OSD font addresses are produced. Next, the OSD fonts is read and delivered to the decoder. Further, the decoder performs a decoding process for the OSD fonts to form a plurality of rotated fonts. The OSD message, including the rotated fonts, is displayed on a display device so that the video display is synchronized with the OSD message.

Abstract: This invention provides a method for automatically adjusting the sampling phase of a LCD control system. This method uses a special function to compute the image characteristic values under different sampling phases and to select the sampling phase with the largest image characteristic value as the correct sampling phase.

Abstract: An image dithering device processing in both time domain and space domain to improve the image quality of an LCD digital display is disclosed. The device comprises a Gamma Table for performing Gamma processing on input signals; a counter module for generating a row counting value and a column counting value by counting the vertical synchronizing signal, horizontal synchronizing signal, and image pixel clock of the LCD image control system; a dithering value generating module for providing a dithering value for each pixel according to the row counting value and the column counting value, the dithering value generating module having a matrix with different value; and a calculation module for performing calculation on the value output form the Gamma Table and the dithering value for decreasing the bits of the input image value so as to fit the input data bits of the LCD display.

Abstract: A method and apparatus is provided for interpolating a digital image in response to a requested degree of sharpness. An adjusting signal representing the requested degree of sharpness will then be generated. The interpolated pixel data are computed based on a two-order interpolation function for two sampling input pixels with an adjustable weight coefficient representing the selected degree of sharpness. The apparatus of the present invention mainly includes: a control interface, a control unit, a vertical interpolation computation module, and a horizontal interpolation module. The vertical interpolation computation module and the horizontal interpolation module are implemented according to an interpolation function derived by the present invention. The control unit comprises a lookup table built according to a scaling function of the present invention.

Abstract: An analog-to-digital converter receives slow-varying analog voltages from a sensing device and converts the slow-varying analog voltages to digital signals. The sensing device generates a slow-varying analog voltage directly proportional to absolute temperature. The analog-to-digital converter includes a second counter which receives the pulse train from the second voltage controlled oscillator that counts the number of pulses which informs the first counter whenever the count value thereof reaches a fixed number and resets the count value thereof to zero. As the first counter is being informed by the second counter, its count value is read and then reset to zero. The read count represents a digital signal corresponding to the slow-varying analog voltages input.

Abstract: The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI.

Abstract: The object of present invention is to provide a programming switch for non-volatile memory wherein output voltage Vout versus input voltage Vin satisfies the following relations: (1) While Vin is logic "0", Vout is logic "0"; (2) While Vin is logic "1", Vout is about the value of programming voltage Vpp if programming is executed and about the value of supply voltage Vcc if programming is not executed. The present invention is characterized in that it can be utilized in general non-volatile memory and the supply voltage needed can be as low as 2 volts, resulting in body effect almost giving no influence.

Abstract: A waveform shaping circuit includes an input terminal, an output terminal, and a plurality of cascaded circuit stages. Each of the cascaded circuit stages includes a delay circuit having an output and an input, a current source, and a switch circuit, connected electrically to the output of the delay circuit and controlled by the delay circuit, for connecting electrically the current source to the output terminal. The input of the delay circuit of a first one of the circuit stages is connected electrically to the input terminal. The input of the delay circuit of remaining ones of the circuit stages is connected electrically to the output of the delay circuit of an immediately preceding one of the circuit stages. The delay circuits have equal delay times. The total delay time provided by the delay circuits of the circuit stages is equal to or is a multiple of half a bit time of the fundamental data rate.

Abstract: The present invention provides a security configuration of EEPROM, which is adaptable to a semiconductor integrated circuit. Each byte or minimum cell of the EEPROM is assigned a security bit which corresponds to the same memory cell of EEPROM in a data memory array. Since the security bit can be established inside the memory array, necessary chip area is not increased significantly.

Abstract: A non-volatile memory array includes a plurality of memory cells. Each of the memory cells stores two-bits of data therein and has a threshold voltage corresponding to the data bits stored therein. A voltage providing unit provides a first test voltage to an addressed one of the memory cells. A sensing unit senses whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein. When the first bit of data stored in the addressed one of the memory cells is 0, the voltage providing unit provides a second test voltage and the sensing unit senses whether the addressed one of the memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein.

Abstract: A driver circuit is to be used with an attachment unit interface in a network system and receives complementary data signals and an enable signal from constant current source and a differential transistor pair which includes a pair of differential transistors and a pair of load resistors. Each of the differential transistors has a gate terminal which receives one of the complementary data signals, a drain terminal which is connected to one of the load resistors, and a source terminal which is connected to the constant current source. A switch network is connected to the drain terminal of the differential transistors and is activated by the enable signal so as to generate a differential voltage output. Each of a pair of source followers has a gate terminal connected to the switch network and a source terminal The source followers receive the differential voltage output from the switch network.

Abstract: A television game console has a central processing unit and an electronic control device for controlling the allowable playing time of the television game console. The electronic control device includes a timer control device which interfaces the central processing unit with a game cartridge read only memory unit. The timer control device has a current time clock output and receives a presettable allowable playing time range input from the central processing unit. The timer control device electrically connects the game cartridge read only memory unit and the central processing unit only when the current time clock output is within the allowable playing time range.

Abstract: An integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 500.degree. C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of the said antifuse layer in excess of 500.degree. C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti.sub.5 Si.sub.3, TiSi, and/or TiSi.sub.2 than is yielded TiO, Ti.sub.2 O.sub.3, Ti.sub.3 O.sub.5, and/or TiO.sub.2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.