Abstract: A modular foundation design for supporting a wind turbine or telecommunication tower, comprised of pre-cast concrete modules offering advantages of off-site manufacture and ease of transportation, but which deign is simple to construct. A base slab is provided comprised of sub-modules/base members arranged together in juxtaposed position which together provide a horizontal surface on which pre-cast pipe members may be stacked in end-to-end position to form a pedestal. Anchor rods extend through the pipe members into screw retainers in the base members, which rods serve to not only post-tension the pipe members and secure them together, but further advantageously serve to retain the base members together thereby assisting in distributing forces and loads applied to one sub-module/base member over the entire base slab. Coupling means to further couple the base members together may be added to better retain the base members together and still further improve distribution of forces.

Abstract: A non-straight sensor array within a gravity field, within a surface and cyclically surrounding a medial axis. The sensor array includes rigid bodies holding gravimetric tilt sensors, the rigid bodies being connected by flexible joints. The flexibility of the joints is constrained to two degrees of freedom. The shape of the path, the surface, and the medial axis are measured in at least two dimensions, using the tilt sensor data and the geometrical constraints of the joints. The cyclical geometry permits simultaneous measurement of lateral and axial deformations in deployments varying from axially vertical to axially horizontal, as well as improved fit of the array to surrounding surfaces. The field of use includes geotechnical measurements of soil and civil structures.

Abstract: A bipartite sensor array comprising two portions capable of assembly into a single sensory system. A first portion includes rigid bodies connected by elongate flexures and fitted with gravimetric tilt sensors. The elongate flexures are capable of non-monotonic and non-constant bend in two degrees of freedom. A second portion includes rigid bodies connected by joints, contains the first portion. The second portion, which may be delivered and assembled separately from the first, provides rigidity and protection, enabling the first portion to have short rigid bodies and long connecting flexures, thereby reducing the number of sensors required. The bipartite sensor array is applicable to geotechnical measurements of soil and civil structures.

Abstract: A non-straight sensor array within a gravity field, within a surface and cyclically surrounding a medial axis. The sensor array includes rigid bodies holding gravimetric tilt sensors, the rigid bodies being connected by flexible joints. The flexibility of the joints is constrained to two degrees of freedom. The shape of the path, the surface, and the medial axis are measured in at least two dimensions, using the tilt sensor data and the geometrical constraints of the joints. The cyclical geometry permits simultaneous measurement of lateral and axial deformations in deployments varying from axially vertical to axially horizontal, as well as improved fit of the array to surrounding surfaces. The field of use includes geotechnical measurements of soil and civil structures.

Abstract: A bipartite sensor array comprising two portions capable of assembly into a single sensory system. A first portion includes rigid bodies connected by elongate flexures and fitted with gravimetric tilt sensors. The elongate flexures are capable of non-monotonic and non-constant bend in two degrees of freedom. A second portion includes rigid bodies connected by joints, contains the first portion. The second portion, which may be delivered and assembled separately from the first, provides rigidity and protection, enabling the first portion to have short rigid bodies and long connecting flexures, thereby reducing the number of sensors required. The bipartite sensor array is applicable to geotechnical measurements of soil and civil structures.

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the res

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Abstract: An engine controller for an engine configured for improving fuel economy and decreasing negative emission characteristics. The engine controller is operatively coupled to the engine and configured to intercept angular position sensor signals and generate an adjustable angular position sensor signal and output the adjusted signal to the engine control module operatively coupled to the engine. The engine control module is configured to control the fuel injector for the engine and is responsive to the adjusted angular position sensor signal. The engine controller is operatively coupled to a hydrogen injection module configured to deliver hydrogen to the engine in conjunction with the operation of the engine controller. According to another aspect, the engine controller is configured to intercept valve actuator signals from the engine control module intended to control variable valve actuators in the engine.

Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.

Abstract: A semiconductor memory device having semiconductor memory chips, each semiconductor memory chip includes a plurality of memory banks capable of independently to be accessed, each memory bank having a plurality of memory blocks, wherein at least two memory blocks, which are neighbored each other in the same memory bank, have the different number of unit memory blocks, so that each bank has a non-rectangular shape.

Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.

Abstract: A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the res

Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.