Abstract: Disclosed are a multi-mode virtual serial port chip, an implementation method, and a firmware downloading system and method thereof. The multi-mode virtual serial port chip comprises a normal operating mode and an enhanced operating mode, which are selected by a multiplexed auxiliary signal pin according to that whether there is a pull-down resistor connected thereto. The normal operating mode is compatible with the prior art and applications, and one-click automatic MCU firmware downloading can also be realized in the enhanced operating mode. In the present invention, no peripheral circuit is needed, the MCU also cannot unintentionally enter other modes, and the effects of automatically downloading firmware, improving downloading efficiency, reducing costs, reducing power consumption and decreasing product volume are achieved.

Abstract: Disclosed are a multi-mode virtual serial port chip, an implementation method, and a firmware downloading system and method thereof. The multi-mode virtual serial port chip comprises a normal operating mode and an enhanced operating mode, which are selected by a multiplexed auxiliary signal pin according to that whether there is a pull-down resistor connected thereto. The normal operating mode is compatible with the prior art and applications, and one-click automatic MCU firmware downloading can also be realized in the enhanced operating mode. In the present invention, no peripheral circuit is needed, the MCU also cannot unintentionally enter other modes, and the effects of automatically downloading firmware, improving downloading efficiency, reducing costs, reducing power consumption and decreasing product volume are achieved.

Abstract: An anti-fuse memory cell and a data read-write circuit thereof. The anti-fuse memory cell comprises a base, the base is provided with an N-well and a non-N-well region; the non-N-well region is provided with a first NMOS transistor; a gate of the first NMOS transistor is used for inputting a first selection signal; the N-well is provided with a PMOS transistor and a varactor; a gate of the PMOS transistor and a gate of the varactor are both connected to a drain of the first NMOS transistor; and a drain, a source and a substrate of the PMOS transistor and a drain, a source, and a substrate of the varactor are all connected to a controllable power supply.

Abstract: A interrupt control system and method based on RISC-V comprises a processor, a fast interrupt controller, a Caller-save type general-purpose register, and a hardware memory area; the hardware memory area is used for storing a value of the Caller-save type general-purpose register during an interrupt response; and the fast interrupt controller is used for storing the value of the Caller-save type general-purpose register into the hardware memory area, or loading back a content from the hardware memory area into the Caller-save type general-purpose register, and further storing a value of a control and status register set into the hardware memory area when a nested interrupt occurs; which improve an interrupt handling speed of a RISC-V architecture processor, simplify the program development difficulty, expand an application field of the RISC-V as a core single chip microcomputer, and particularly have a wide prospect in the embedded application field.

Abstract: An USB multiplexing single-wire interface unit comprises a D+ pin, a D? pin, a control bit register for USB and single-wire interface modes and a USB controller, the USB controller comprises an EOP detection module and a single-wire interface EOP detection module. The USB mode or the single-wire interface mode is selected according to mode identification of the control bit register for USB and single-wire interface modes, an output of the EOP detection module is selected as a USB EOP trigger signal in the USB mode, and an output of the single-wire interface EOP detection module is selected as a USB EOP trigger signal in the single-wire interface mode.

Abstract: A decoding implementation method of a Bluetooth receiver includes: setting a first length threshold and a second length threshold; decoding and backtracking a first FEC block, and outputting a coded indicator and an access address of the first FEC block; determining whether a second FEC block needs despreading according to the coded indicator; matching the access address with an actual address, storing a survivor-path of the second FEC block in a SMU, decoding and backtracking the data stored in the SMU, outputting bit information, and taking out a length of a packet payload in a packet header from a time; and judging whether a total number of bits of the second FEC block exceeds the second length threshold according to the length of the packet payload to complete decoding.