Abstract: Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable.

Abstract: The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS) and a top-down shape (TDS). The BUS and TDS are merged to form a final geometrical Middle Shape (MS). Each point in the MS has a position is averaged from the positions of the two correlated points in the BUS and TDS. Unnecessary short jogs are removed from the MS of each wire. A final layout is generated by combining all of the final geometric shapes of each wire segments. As such, the wire-to-wire spacing is increased to more than the minimum spacing requirement without causing any design rule violations.

Abstract: The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.