Patents Assigned to Nano Silicon Pte Ltd.
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Patent number: 7170963Abstract: The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used for data sampling, a phase clock that lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during sampling. This system is less complex and consumes minimal power over systems using variable delay circuits.Type: GrantFiled: January 15, 2003Date of Patent: January 30, 2007Assignee: Nano Silicon Pte. Ltd.Inventor: Jiao Meng Cao
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Patent number: 7154150Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n?/p?/n?/n+ regions. The emitter is formed of the second N+ region and the second N? well. The parasitic base is formed by the p? substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n? well (emitter) and P? substrate (base) and the junction between P? substrate (base) and the n? well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region.Type: GrantFiled: August 26, 2004Date of Patent: December 26, 2006Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai
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Patent number: 7009435Abstract: Output buffer slew rate variation over variations in load capacitance is minimized by dividing output voltage transitions into distinct time and output current segments. During the first time segment, the first drive stage with the smallest current is employed. After subsequent delays, additional drive stages are employed and the load current is sequentially increased. Each drive stage employs a specifically sized feedback device which, depending upon its dimensions will provide either parasitic capacitance to slow transitions or positive feedback to speed up transitions. The first stages are sized to incorporate parasitic capacitance, resulting in little change in the settling time of small capacitance loads over prior art output buffers. Latter stages use positive feedback to quicken the transition time which dramatically improves the settling time for larger load capacitances over prior art output buffers.Type: GrantFiled: March 9, 2004Date of Patent: March 7, 2006Assignee: Nano Silicon Pte Ltd.Inventors: Jun Ho Cho, Hong Sair Lim
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Patent number: 6787880Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.Type: GrantFiled: May 13, 2003Date of Patent: September 7, 2004Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai
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Patent number: 6787856Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.Type: GrantFiled: July 22, 2002Date of Patent: September 7, 2004Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai
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Publication number: 20040135711Abstract: The present invention is a serial to parallel data conversion method and device where new serial data are stored within a first n-bit register prior to presentation at an n-bit parallel output. Subsequently, additional data are stored within a second n-bit register while the data stored within the first register are presented at the parallel output. Data storage and data presentation are thereafter alternated, thereby eliminating the problem of setup time seen in prior art.Type: ApplicationFiled: January 13, 2003Publication date: July 15, 2004Applicant: Nano Silicon Pte. Ltd.Inventor: Wu Guosheng
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Publication number: 20040136483Abstract: The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used for data sampling, a phase clock that lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during sampling. This system is less complex and consumes minimal power over systems using variable delay circuits.Type: ApplicationFiled: January 15, 2003Publication date: July 15, 2004Applicant: Nano Silicon Pte. Ltd.Inventor: Jiao Meng Cao
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Patent number: 6762560Abstract: The present invention is a serial to parallel data conversion method and device where new serial data are stored within a first n-bit register prior to presentation at an n-bit parallel output. Subsequently, additional data are stored within a second n-bit register while the data stored within the first register are presented at the parallel output. Data storage and data presentation are thereafter alternated, thereby eliminating the problem of setup time seen in prior art.Type: GrantFiled: January 13, 2003Date of Patent: July 13, 2004Assignee: Nano Silicon Pte. Ltd.Inventor: Wu Guosheng
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Publication number: 20040114637Abstract: This invention provides a circuit and a method for very high-speed multiplexers. It provides a circuit that can produce an arbitrary number of multiple signal multiplexers. It also provides a circuit and a method which converts a parallel data bus into a serial data path. This invention contains an overlapped data generator, which takes in a data bus and outputs even and odd signals to a selective mux. It also contains a selective mux, which receives even and odd internal data bits from said overlapped data generator and which outputs one serial data bit. It also contains a phase locked loop/delay locked loop, PLL/UDLL, which receives a set of phase clocks and which outputs five evenly-phase-distributed clock signals to a data select signal generator. Finally, the circuit includes a data select signal generator, which receives said five evenly-phase-distributed clock signals and which generates a ten-bit data select signal bus.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: Nano Silicon Pte. Ltd.Inventor: Bian Jiang
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Patent number: 6589833Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.Type: GrantFiled: December 3, 2001Date of Patent: July 8, 2003Assignee: Nano Silicon Pte Ltd.Inventors: David Hu, Jun Cai
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Publication number: 20030102487Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.Type: ApplicationFiled: July 22, 2002Publication date: June 5, 2003Applicant: Nano Silicon Pte,Ltd.Inventors: David Hu, Jun Cai
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Patent number: 6507090Abstract: A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p+ diffusion region. The emitter and the substrate act as a first diode D1 and the collector and the substrate act as a second diode D2. The second embodiment has a first N+ well between a second n+ (collector) region and a P+ base region. The Vt1 is controlled by the dopant profiles of the P+ base and the n− first well where they intersect. The third embodiment is similar to the second embodiment, but the n− well covers all of drain. A parasitic NPN bipolar transistor comprises: an emitter, a parasitic base and a drain. The emitter is formed by the first n+ region. The parasitic base is formed by the p-substrate.Type: GrantFiled: December 3, 2001Date of Patent: January 14, 2003Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai
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Patent number: 6444510Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n− well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.Type: GrantFiled: December 3, 2001Date of Patent: September 3, 2002Assignee: Nano Silicon Pte. Ltd.Inventors: David Hu, Jun Cai