Abstract: Embodiments feature techniques and systems for analog and digital tuning of crystal oscillators. In one aspect, some implementations feature a method for tuning a frequency of a crystal oscillator that can include adjusting the tuning frequency of the crystal oscillator from a nominal frequency via a switched-capacitor frequency tuning circuit, the switched-capacitor frequency tuning circuit can have switchable sections to adjust the tuning of the crystal oscillator. The method can include controlling an analog control input that is coupled to a varactor within each of the switchable sections, where each of the switchable sections can include a fixed capacitor in series with the varactor and a switch. The method can involve controlling a digital control input, where the digital control input can electrically connect or disconnect one or more of the switchable sections from the crystal. There can be independent control between the digital and analog tuning mechanisms.

Abstract: Systems, circuits, and techniques for the calibration and fast tuning of VCOs in PLLs are provided. Information for coarse tuning before normal operation are calculated and stored. These systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques involve: determining a digital code Dc, to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, these systems and techniques involve: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.

Abstract: Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

Abstract: A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

Abstract: Two or more low noise amplifiers are configured to amplify received radio frequency input signals and one or more shared load or source degeneration inductors are configured to be used for each of the two or more low noise amplifiers. Further, the one or more shared inductors can be configured to be used for processing two or more signal bands in a multi-band communication system.

Abstract: A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal. A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal. An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms. Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard.

Abstract: A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.

Abstract: At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.

Abstract: Techniques and systems for receiving a signal at a first component with an adjustable gain, and adjusting the gain of the first component to a first gain value using a first gain step. Amplifying the signal with the first gain value, generating a first amplified signal, and receiving the first amplified signal at a second component with an adjustable gain. Adjusting a gain of the second component to a second gain value using a second gain step. The net gain step is smaller than one of the first or second gain step. Amplifying the first amplified signal with the second gain value to generate a second amplified signal, and receiving the second amplified signal at a filtering component. A transient response introduced by the filtering component on the second amplified signal is smaller than the transient response that would be introduced by the filtering component on the first amplified signal.

Abstract: Embodiments feature a circuit that includes a first set of differential switches to generate a first mixer output. The first set includes source terminals, a differential input terminal, gate terminals, and first mixer output terminals. For the first set, the source terminals are coupled to the differential input terminal and the gate terminals are coupled to a first differential oscillator input. The circuit includes a second set of differential switches to generate a second mixer output. The second set of differential switches has source terminals, gate terminals, and second mixer output terminals. For the second set of differential switches, the source terminals of the second set of differential switches are coupled to the first mixer output terminals to receive the first mixer output and the gate terminals of the second set of differential switches are coupled to a second differential oscillator input. The second mixer output terminals couple a filter.

Abstract: The present invention provides novel methods for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these methods decrease significantly the time needed for a PLL to transition from one frequency to another. These methods include the steps of: determining a digital code Dc to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency, F.

Abstract: A multiple frequency RF communications receiver is disclosed which permits greater integration on standard silicon chips and consumes less power than previous receivers. A new method for selecting the various frequency bands with a high amount of isolation and low power consumption is described. Compared to previous receiver implementations, there is no loss of selectivity in the receiver.

Abstract: A mixer design is described that permits greater integration on standard silicon chips with an improvement in power and linearity compared to previous mixer designs, enabling low-power, high performance RF reception.

Abstract: To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals represent addresses of defective memory cells in the ROM. An ADDHIT signal indicates that the ROM has received an address of a defective memory cell. The ADDHIT signal is then timed to provide a REV signal that changes the polarity of the memory bit signal out of a buffer circuit. This corrects an erroneous memory cell by reversing the sense of the memory bit received from a defective memory cell and delivered to an output terminal of the ROM. The REV signal is steered to an output buffer corresponding to the proper ROM chip output pad using a fuse-controlled selection circuit.

Abstract: A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a test-mode enable circuit, an arbitration circuit, and a memory control logic circuit. In a normal mode of operation, the test mode enable circuit is not active. In a test mode of operation, the test mode enable circuit is active which enables the memory control logic to be controlled by an external command signal that is provided through an external pin, such as a chip-enable /CE pin when the chip is in the test mode.

Abstract: A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is a multi-media RAM (MMRAM) chip that provides on a single integrated-circuit chip a memory array and a compressor/decompressor (CODEC) section where connections between the memory array section and the CODEC section are on the single integrated-circuit die. The smart memory eliminates the need for additional special function integrated-circuit packages and significantly reduces the clock rate and the power consumption of a baseband chip in a personal communication device.

Abstract: A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh request control signal to initiate an internal refresh cycle. A refresh-request storage element is reset upon initiation of an internal refresh cycle. A refresh miss detector provides an output pulse when the refresh request signal is received concurrent with the refresh request storage element being set. Provision is made to read out the count, and to reset the count. By reading out the count an indication is obtained of how many refresh requests were missed, and by using arbitrary input patterns the robustness of the self-refreshing DRAM is improved.

Abstract: Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

Abstract: A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide an improved, combined power-up control signal CPWRUP. The combined power-up control signal CPWRUP signal is temporarily brought to a LOW state for a predetermined period of time immediately after the end of a power-saving mode of operation, such as a deep-sleep mode of operation for a memory device. The LOW state of the combined power-up control signal CPWRUP output signal allows all internal circuitry to be returned to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.

Abstract: An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a drain boost capacitor and to a drain precharge circuit. The gate boost capacitor is precharged from the common VCC voltage. The second terminal of the precharged gate boost capacitor is connected to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC. The drain of the NMOS pass transistor has a similar boost capacitor and precharge configuration. Another embodiment further includes an additional gate preboost capacitor and a gate preboost precharge circuit for boosting the gate voltage to 3 VCC to more efficiently drive the NMOS pass transistor.