Abstract: Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

Abstract: Embodiments feature techniques and systems for analog and digital tuning of crystal oscillators. In one aspect, some implementations feature a method for tuning a frequency of a crystal oscillator that can include adjusting the tuning frequency of the crystal oscillator from a nominal frequency via a switched-capacitor frequency tuning circuit, the switched-capacitor frequency tuning circuit can have switchable sections to adjust the tuning of the crystal oscillator. The method can include controlling an analog control input that is coupled to a varactor within each of the switchable sections, where each of the switchable sections can include a fixed capacitor in series with the varactor and a switch. The method can involve controlling a digital control input, where the digital control input can electrically connect or disconnect one or more of the switchable sections from the crystal. There can be independent control between the digital and analog tuning mechanisms.

Abstract: Systems, circuits, and techniques for the calibration and fast tuning of VCOs in PLLs are provided. Information for coarse tuning before normal operation are calculated and stored. These systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques involve: determining a digital code Dc, to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, these systems and techniques involve: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.

Abstract: Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

Abstract: A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

Abstract: Circuits and methods for a mixer circuit involve having a first transistor with first and second terminals, where the first terminal is configured to handle an input RF signal. The mixer has a second transistor including a first terminal coupled to the second terminal of the first transistor, a second terminal configured to handle an input oscillator signal, and a third terminal configured to output an intermediate frequency (IF) signal. The IF signal includes a mixed product of the input RF signal and the input oscillator signal. A gate oxide thickness of the first transistor is less than a gate oxide thickness of the second transistor to provide enhanced linearity and a low noise figure. One or more of the mixers can be implemented in a receiver design.

Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.

Abstract: In some implementations, a signal is received at a device and a gain change is detected in a component of the device that affects the signal. A state of an equalizer is adjusted in response to the detected gain change to a first state that reduces transient effects introduced into the signal by one or more components in the device as a result of the gain change. The signal is equalized using the equalizer with the state set to the first state and the state of the equalizer is adjusted from the first state to a second state while equalizing the signal using the equalizer such that the second state passes the signal through the equalizer substantially unchanged.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Two or more low noise amplifiers are configured to amplify received radio frequency input signals and one or more shared load or source degeneration inductors are configured to be used for each of the two or more low noise amplifiers. Further, the one or more shared inductors can be configured to be used for processing two or more signal bands in a multi-band communication system.

Abstract: A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.

Abstract: A receiver includes a common-gate low noise amplifier (LNA) configured to receive an RF input signal and produce an amplified RF signal. A down-converting passive mixer is configured to mix the amplified received RF input signal with a local oscillator signal generated by a local oscillator to generate a down-converted amplified signal. An amplifier is configured to amplify the down-converted signal and has an input impedances in on the order of ohms. Only a single LNA may be required to receive RF inputs in all frequency bands of a multi-band communication standard.

Abstract: Radio frequency filtering includes receiving a signal and detecting a change in the direct current (DC) offset of the signal or a change in a component that affects the DC offset of the signal. The filtering also includes setting a cut-off frequency of a high-pass filter to a first frequency value in response to the detected change and filtering the signal using the high-pass filter with the cutoff frequency set to the first frequency value. The filtering further includes adjusting the cutoff frequency of the high-pass filter from the first frequency value to a second frequency value while filtering the signal using the high-pass filter where the second frequency value is less than the first frequency value.

Abstract: Generally, implementations provide a circuit framework that uses phase and amplitude modulation with several voltage-controlled-oscillators (VCOs) and corresponding variable gain amplifiers (VGAs) to generate and amplitude and phase modulated signals that are summed to an output signal for a transmitter circuit. The implementations can involve decomposing an input signal into a number of decomposed signals using a signal decomposer component, in which each of decomposed signals includes phase and amplitude information. The signal decomposer component can interact with each of the VCOs and corresponding VGAs to conduct the phase and amplitude modulation for the amplitude and phase modulated signals. The multiple standard transmitter circuit can be used for one or more communication standards, such as Global System for Mobile Communications (GSM), a Wideband Code Division Multiple Access (WCDMA), or High-Speed Uplink Packet Access (HSUPA), among others.

Abstract: A signal is received and whether a signal mode of the signal is a first signal mode or a second signal mode is determined. A gain of a variable gain amplifier is adjusted to a first gain value if the signal mode of the signal is determined to be the first signal mode or a second gain value if the signal mode of the signal is determined to be the second signal mode. The signal is amplified with the variable gain amplifier by the first gain value or the second gain value. The signal is converted to a digital signal with an analog to digital converter after the signal is amplified with the variable gain amplifier by the first gain value or the second gain value.

Abstract: At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.

Abstract: A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.

Abstract: A filter is configured to receive a filter charging signal and to produce a filter output signal based on the filter charging signal. The filter includes an element array with one or more switched elements which include an element and a switch configured to connect the element to or disconnect the element from the array, thereby altering a time constant of the filter. A comparator is configured to receive the filter output signal and a reference signal corresponding to a value of the filter output when the time constant has a defined value, and to generate a comparator output signal based on a comparison of the filter output signal to the reference signal. A controller is configured to receive the comparator output signal and, based on the comparator output signal, output an array control signal configured to adjust one or more switches of the one or more switched elements of the element array to alter the time constant such that a value of the time constant approaches the defined value.