Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.
Type:
Grant
Filed:
April 14, 1983
Date of Patent:
July 2, 1985
Assignee:
Nanodata Computer Corporation
Inventors:
Gideon Frieder, David T. Hughes, Mark H. Kline, John T. Liebel, Jr., David P. Meier, Edward A. Wolff
Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.
Type:
Grant
Filed:
December 5, 1980
Date of Patent:
May 7, 1985
Assignee:
Nanodata Computer Corporation
Inventors:
Gideon Frieder, David T. Hughes, Mark H. Kline, John T. Liebel, Jr., David P. Meier, Edward A. Wolff
Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.
Type:
Grant
Filed:
October 11, 1979
Date of Patent:
October 12, 1982
Assignee:
Nanodata Computer Corporation
Inventors:
Gideon Frieder, David T. Hughes, Mark H. Kline, John T. Liebel, Jr., David P. Meier, Edward A. Wolff