Abstract: A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.

Abstract: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.

Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.

Abstract: Deposited layers are advantageously obtained by utilizing a specific hydride vapor phase epitaxy deposition procedure. In this procedure, a vertical growth cell structure with extended diffusion layer, a homogenising diaphragm, sidewall purging gases, anal independent gas and substrate heaters is used for the deposition of III-V and VI compound semiconductors. This gas flow is uniformly mixed through the extended diffusion layer and directed so that it contacts the full surface of the substrate to produce high quality and uniform films. Exemplary of such gas flow configurations are the positioning of a substrate at a distance from the gas outlets to allow the extended diffusion and a diaphragm placed in a short distance above the substrate to minimize the impact of the convection effect and to improve the uniformity. This symmetrical configuration allows easy scale up from a single wafer to multi-wafer system.