Abstract: New types of circuit elements for integrated circuits include structures wherein a thickness dimension is much greater than a width dimension and is more closely spaced than the width dimension in order to attain a tight coupling condition. The structure is suitable to form inductors, capacitors, transmission lines and low impedance power distribution networks in integrated circuits. The width dimension is on the same order of magnitude as skin depth. Embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral trench. Other embodiments include a wide, thin conductor formed in or on a flexible insulative ribbon and wound with turns adjacent one another, or a conductor in or on a flexible insulative sheet folded into layers with windings adjacent one another Further, a method of manufacture includes directional etching of the deep, narrow spiral trench to form a winding in silicon.

Abstract: New types of circuit elements for integrated circuits include structures wherein a thickness dimension is much greater than a width dimension and is more closely spaced than the width dimension in order to attain a tight coupling condition. The structure is suitable to form inductors, capacitors, transmission lines and low impedance power distribution networks in integrated circuits. The width dimension is on the same order of magnitude as skin depth. Embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral trench. Other embodiments include a wide, thin conductor formed in or on a flexible insulative ribbon and wound with turns adjacent one another, or a conductor in or on a flexible insulative sheet folded into layers with windings adjacent one another Further, a method of manufacture includes directional etching of the deep, narrow spiral trench to form a winding in silicon.

Abstract: A method is provided for fabricating thick silicon oxide structures, such as an embedded inductor. A Deep Reactive Ion Etch (DREI) etches the top silicon layer of a substrate to form high aspect ratio Si features, called trench texturing. The Si features are oxidized to form silicon oxide features. Adjacent Si features are separated by a trench width (S(0)), so that after oxidation, adjacent Si oxide features are formed separated by trench width (S(t)), where S(t)?S(0) (e.g., S(t)=0). If the Si features have a width WSi(0)>1.2728 S(0), then the adjacent silicon oxide features form an amorphously merged silicon oxide feature with a planar top surface. The silicon oxide features have a height (HOX(t)) responsive to the trench width (S(0)), the Si feature width (WSi(t)), and the Si feature aspect ratio. After oxidation, inductor metal is deposited in trenches where WSi(0)<1.2728 S(0).

Abstract: A system and method are provided for supplying bulk current to a voltage regulator embedded on a system-on-chip (SoC). An embedded voltage regulator (EVR) supplies a regulated voltage to a functional unit, the current demand is determined, and a current control signal is generated. An off-SoC bulk current source accepts the current control signal and supplies auxiliary (bulk) current to the functional unit in response to the current control signal. For example, in a first period of time a dynamic increase demand for a first current. Initially the EVR supplies the first current and creates an increase in SoC thermal loading. Subsequently, the EVR supplies a current less than the first current while the bulk current source supplies the bulk of the current. As a result, the bulk current source creates an off-SoC thermal load.