Abstract: A solid state RADAR antenna system is provided comprising at least one antenna configured to transmit a plurality of antenna beams. Each antenna beam is decoupled from each of the other plurality of antenna beams for transmitting in a blind range of a different antenna beam. Accordingly, in an implementation, the second antenna beam is transmitted so as to scan a first blind range associated with the first antenna beam. Decoupling antenna beams can be achieved using one or more of physical decoupling using different antennas, frequency decoupling using different bands and/or frequency multiplexing, or orthogonal polarization.

Abstract: A RADAR antenna system and method are provided. In an implementation, the system includes a base and first and second antennas configured to transmit independent first and second antenna beams, respectively. The first and second antennas are each coupled to the base so as to provide a common rotational axis for the first and second antennas. An antenna position controller is configured to independently control first and second transmission positions associated with the first and second antennas, respectively. Two different antenna technologies can be used, for example one for providing communications capability and the other for providing tracking capability. Other implementations include four or more antennas configured to transmit beams at similar or different frequencies. Improvements in scan rate proportional to the number of antennas are achieved compared to that achievable with a single beam, without an increase in the rotation rate of the antenna system.

Abstract: Disclosed herein is a system and method for determining a thickness of ice on Radio Frequency (RF) systems The system includes a sensor unit for use in determining the thickness of ice on a surface of a RADAR system having a RADAR antenna, the sensor unit including a sensor unit antenna tunable to a harmonic of a RADAR antenna signal, the harmonic having a frequency within an ice absorption band, wherein the sensor unit antenna emits the harmonic at a first signal strength; and, a sensor unit receiver communicatively coupled to the sensor unit antenna and configured to detect a second signal strength of the harmonic received by the sensor unit antenna.

Abstract: A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

Abstract: A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

Abstract: An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.

Abstract: An optoelectronic oscillator (OEO) is disclosed comprising an electronically tunable filter for transposing narrow pass band characteristics of a surface acoustic wave (SAW) filter to a microwave frequency to provide mode selection in the OEO. An OEO is disclosed comprising a set of optical domain components, a downconverter in communication with an output of the optical domain components, and a set of radio frequency (RF) domain components in communication with an output of the downconverter. The set of RF domain components comprises a tunable filter operating at a filter center frequency and having an output coupled to the set of optical domain components for communicating a mode selection result. The tunable filter including a tuner; and a sub-filter. The sub-filter operating at a fixed center frequency to provide mode selection and adjacent mode suppression with respect to the tunable filter center frequency.

Abstract: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.

Abstract: Embodiments disclosed herein relate to wave guide couplers as well as 3-way, 6-way, and 9-way combiners. The waveguide coupler comprises: a housing having a first outer waveguide branch, a second outer waveguide branch, and an inner waveguide branch; first, second, and third input ports in communication with the first outer, second outer, and the inner waveguide branches respectively; an output port in communication with the inner waveguide branch; a first wall separating the first outer waveguide branch and the inner waveguide branch, the first wall having a first iris; a second wall separating the second outer waveguide branch and the inner waveguide branch, the second wall having a second iris; a first tapered section in the first outer waveguide branch; and a second tapered section the second outer waveguide branch. Various embodiments of the 3-way, 6-way, and 9-way combiners are implemented using the wave guide coupler.

Abstract: A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phased locked loop (PLL), the phased locked loop comprising: a phase frequency detector, an oscillator, and a PLL output coupled to the output; a first direct digital synthesizer (DDS), the first DDS having an output coupled to the PLL to supply a DDS signal to the PLL for adjusting the frequency within the PLL so as to maintain phase lock over the operating temperature; a temperature sensor; and a processor coupled to the first DDS, the phase frequency detector, and the temperature sensor, the processor configured to set the frequency of the first DDS according to a temperature sensed by the temperature sensor.

Abstract: A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phased locked loop (PLL), the phased locked loop comprising: a phase frequency detector, an oscillator, and a PLL output coupled to the output; a first direct digital synthesizer (DDS), the first DDS having an output coupled to the PLL to supply a DDS signal to the PLL for adjusting the frequency within the PLL so as to maintain phase lock over the operating temperature; a temperature sensor; and a processor coupled to the first DDS, the phase frequency detector, and the temperature sensor, the processor configured to set the frequency of the first DDS according to a temperature sensed by the temperature sensor.

Abstract: An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (VCO), the VCO output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed-back input, and an output; a mixer having a first mixer input coupled to the synthesizer input and a second mixer input coupled to the VCO output; a first divider for frequency dividing a signal by a first value and having an input coupled to the mixer output and an output coupled to the second input of the phase frequency detector; a second divider for frequency dividing a signal by a second value and having an input coupled to the synthesizer input and an output coupled to the reference input of the phase frequency detector; and a low pass filter coupled between the output of the phase frequency detector and the VCO input.

Abstract: An electronically tunable filter (ETF) and systems comprising an ETF are disclosed herein. The ETF comprises: a first image rejection mixer; a second image rejection mixer; a first hybrid coupler, the first hybrid coupler being coupled to the first image rejection mixer; a second hybrid coupler, the second hybrid coupler being coupled to the second image rejection mixer; an internal filter coupled to the first hybrid coupler and the second hybrid coupler; a control port for receiving a control signal; a power splitter coupled to the control port, the first image rejection mixer, and the second image rejection mixer; a first port coupled to the first image rejection mixer; and a second port coupled to the first image rejection mixer.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.