Patents Assigned to Naoetsu Electronics Company
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Patent number: 6332833Abstract: A method of fabricating a silicon semiconductor discrete wafer while dressing the grinding wheel is disclosed that assures excellent finishing accuracy and productivity. The dressing of the grinding wheel includes mixing air and grinding water from a surface grinding process including semiconductor chips lapped with abrasive grains having a count of at least #2000 and no more than #6000 and jetting the mixed air and grinding water as minute water drops back onto the surface of the grinding wheel during grinding of a wafer. Both cut surfaces are ground to a predetermined thickness with the dressed grinding wheel (via a surface grinding machine). The processing surface is wet-etched as the final processing.Type: GrantFiled: November 18, 1999Date of Patent: December 25, 2001Assignee: Naoetsu Electronics CompanyInventors: Hisashi Ohshima, Tsutomu Satoh
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Patent number: 6093648Abstract: The problem to be solved by the present invention is providing a production method capable of adjusting a dislocation density freely to a required dislocation density level for a discrete structure substrate. According to the present invention, when producing a discrete structure substrate generally said to have a low level dislocation density in which an average dislocation density is 5000 pieces/cm.sup.2, diffusing a wafer after determining its thickness so as to meet required dislocation density level, a wafer thickness is adjusted within a specified range before diffusion is carried out.Type: GrantFiled: July 13, 1998Date of Patent: July 25, 2000Assignee: Naoetsu Electronics CompanyInventor: Tsutomu Satoh
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Patent number: 6090720Abstract: Wet etching method and apparatus in which a wafer is processed so as to have a good flatness by making uniform a travel distance and a traveling velocity of an arbitrary point on a wafer surface relative to an etching solution, while rotating the wafer in the etching solution. An etching solution vessel comprises a pair of walls parallel to a plane of rotation of a wafer; and walls of curved surfaces, which intersect the pairs of walls at a right angle, and whose centers of curvature are the same, and which are spaced apart from each other along a radius of curvature with a distance of d therebetween; the etching solution is fed from a lower part of the vessel; and a flow velocity of the etching solution is adjusted at an arbitrary point between the pair of curved surfaces just before a stream of the solution contacts with a wafer rotating in the etching solution so that the flow velocity is a velocity (r.omega.Type: GrantFiled: February 6, 1998Date of Patent: July 18, 2000Assignee: Naoetsu Electronics CompanyInventor: Tsutomu Satoh
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Patent number: 6066562Abstract: A method of fabricating a silicon semiconductor discrete wafer is disclosed that assures excellent finishing accuracy and productivity. The method for fabricating a discrete wafer having a double-layer structure including an impurity diffused layer at one side and an impurity non-diffused layer at the opposite side includes cutting a wafer, having one of the impurity diffused layers formed on both surfaces of the silicon semiconductor wafer and having an oxide film formed on the surface of the diffused layer, into two pieces at the center of thickness with an ID saw slicing machine. Then, both surfaces of the cutting surface are ground to a predetermined thickness with a surface grinding machine, and the grinding surfaces are lapped with abrasive grains having a count of at least #2000 and no more than #6000. The processing surface is wet-etched as the final processing.Type: GrantFiled: July 22, 1997Date of Patent: May 23, 2000Assignee: Naoetsu Electronics CompanyInventors: Hisashi Ohshima, Tsutomu Satoh
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Patent number: 5472909Abstract: An efficient method is proposed for the preparation of a silicon single crystal wafer for discrete semiconductor devices, such as transistors, deeply doped with a dopant on one surface, the other surface being mirror-polished.Type: GrantFiled: November 15, 1994Date of Patent: December 5, 1995Assignee: Naoetsu Electronics CompanyInventors: Takeshi Akatsuka, Tsutomu Sato
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Patent number: 5154873Abstract: It is known that it is advantageous in semiconductor wafer production to re-slice a semiconductor wafer having impurity diffusion layers on both sides which are processed or doped in advance of the re-slicing process. In the re-slicing process, a thin slice base is mounted on the periphery of a semiconductor wafer prior to the re-slicing process for protecting the periphery of the wafer from chipping off damage during the re-slicing process by an ID saw or the like. The present invention provides several examples of methods and apparatus for mounting a slice base prepared in advance on the periphery of a semiconductor wafer by utilizing the method and apparatus of the present invention. In addition, another method and apparatus for simultaneously molding and mounting a molded type slice base by using a thermosetting type resin on the periphery of the semiconductor, whereby the re-slicing process of a semiconductor wafer is extremely improved in production and labor cost.Type: GrantFiled: October 1, 1990Date of Patent: October 13, 1992Assignee: Naoetsu Electronics CompanyInventors: Tsutomu Sato, Yasushi Yoshimura
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Patent number: 5142756Abstract: The present invention is directed to an apparatus for loading an unprocessed semiconductor wafer which is doped in advance with impurity diffusion layers on both sides or not doped, re-slicing the wafer and unloading two sheets of the re-sliced wafer as processed wafers upon completion of re-slicing the unprocessed wafer into two sheets to a recovery wafer magazine as a total system. More particularly, the present invention provides an improved loading and unloading mechanism arranged between a storage space of both unprocessed and processed wafers and a re-slicing mechanism, with chucking mechanisms and wafer magazines in the storage space.Type: GrantFiled: October 19, 1990Date of Patent: September 1, 1992Assignee: Naoetsu Electronics CompanyInventors: Tadashi Ibaraki, Tsutomu Sato
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Patent number: 5045505Abstract: When both main surface sides of a substrate doped with an impurity at a lower concentraiton are subjected to diffusion to form a higher concentrated impurity layer on the surfaces, about a half of the thickness of the substrate is removed to expose a layer doped with the impurity at the lower concentration on one surface of the substrate. Then the exposed lower concentrated impurity layer is polished to provide the substrate for semiconductor device comprising double layers composed of higher and lower concentrated impurities.Type: GrantFiled: April 23, 1990Date of Patent: September 3, 1991Assignees: Shin-Etsu Handotai Co., Ltd., Naoetsu Electronics CompanyInventor: Hirokazu Kimura