Patents Assigned to Nascentric, Inc.
  • Patent number: 7970591
    Abstract: In one embodiment, a method for simulating an electric circuit that is represented as one or more partitions, each partition comprising a plurality of constituents representing portions of the circuit, wherein at least one of the constituents is a variable constituent for which the corresponding portion of the electronic circuit includes non-linear behavior, comprises: determining a first matrix for the variable constituent, wherein the first matrix describes a system of equations that represents a behavior of the variable constituent; determining a second matrix for the partition, wherein the second matrix permits calculation of short circuit currents from open circuit voltages according to a node tearing analysis method; and simulating a timestep of the simulation, the simulating comprising iteratively solving a state of the partition using successive guesses of the state of the variable constituent, wherein each iteration comprises solving the variable constituent independently to generate the open circuit
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: June 28, 2011
    Assignee: Nascentric, Inc.
    Inventor: Curtis L. Ratzlaff
  • Patent number: 7444604
    Abstract: A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a linearized circuit model that approximates a behavior of the non-linear circuit element. The computer also inserts into an element matrix a calculated value that corresponds to the linearized circuit model for a prescribed or desired time step. The computer further performs a numerical operation on the element matrix to effectively invert the element matrix.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: October 28, 2008
    Assignee: Nascentric, Inc.
    Inventors: John F. Croix, Curtis Ratzlaff
  • Patent number: 7194716
    Abstract: A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an associated value. Each of the multiple controlled sources has a current value derived from the input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an associated value. The computer is further configured to sweep the values for the input and output stimuli through a two sets of swept values, and to obtain an output current of the model of the circuit as a function of the swept values.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 20, 2007
    Assignee: Nascentric, Inc.
    Inventor: John F. Croix
  • Patent number: 7191414
    Abstract: In one embodiment, a system comprises a computer. The computer is configured to generate a plurality of partial sums corresponding to a first time point of a response on an interconnect, and generate the response at the first time point as a sum of the partial sums. The plurality of partial sums are a function of at least: one or more poles and residues of the interconnect and a time step; wherein at least a first partial sum of the plurality of partial sums is also a function of the first partial sum calculated for a second time point that precedes the first time point.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 13, 2007
    Assignee: Nascentric, Inc.
    Inventor: John F. Croix
  • Patent number: 7155691
    Abstract: A system for analyzing an electronic circuit includes a computer. The computer obtains a description of the electronic circuit. The computer further analyzes the electronic circuit by using compiled static timing analysis (CSTA). Specifically, in one embodiment, the computer is configured to compile a timing model for the circuit responsive to the description of the circuit. The timing model comprises a description of a timing path and a description of an algorithm to evaluate the timing path. The computer is further configured to analyze a design that includes the circuit, wherein the analyzing comprises evaluating the timing model, and wherein evaluating the timing model comprises performing the algorithm to evaluate the timing path.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: December 26, 2006
    Assignee: Nascentric, Inc.
    Inventor: Curtis Ratzlaff
  • Patent number: 7065720
    Abstract: A system for characterizing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input and output. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an output value. The computer is further configured to sweep the input and output values through a first and second set of swept values, and to characterize an output current of the model of the circuit as a function of the first and second swept values.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: June 20, 2006
    Assignee: Nascentric, Inc.
    Inventor: John F. Croix
  • Patent number: 7013440
    Abstract: A system for characterizing an interconnect in an electrical circuit includes a computer. The computer calculates a set of terms, the set of terms derived from (i) a characteristic pole and a characteristic residue of the interconnect and (ii) a fixed time step used to describe a stimulus applied to the interconnect. The computer calculates a response of the interconnect to the stimulus by calculating a partial sum derived from the set of terms.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 14, 2006
    Assignee: Nascentric, Inc.
    Inventor: John F. Croix
  • Publication number: 20040049749
    Abstract: A system for characterizing an interconnect in an electrical circuit includes a computer. The computer calculates a set of terms, the set of terms derived from (i) a characteristic pole and a characteristic residue of the interconnect and (ii) a fixed time step used to describe a stimulus applied to the interconnect. The computer calculates a response of the interconnect to the stimulus by calculating a partial sum derived from the set of terms.
    Type: Application
    Filed: June 19, 2003
    Publication date: March 11, 2004
    Applicants: Silicon Metrics Corporation, SMC Technology, L.L.C., Nascentric, Inc.
    Inventor: John F. Croix
  • Publication number: 20040049748
    Abstract: A system for characterizing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input and output. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an output value. The computer is further configured to sweep the input and output values through a first and second set of swept values, and to characterize an output current of the model of the circuit as a function of the first and second swept values.
    Type: Application
    Filed: June 19, 2003
    Publication date: March 11, 2004
    Applicants: Silicon Metrics Corporation, SMC Technology, L.L.C., Nascentric, Inc.
    Inventor: John F. Croix