Abstract: The present invention discloses a package structure for reducing warpage of plastic package wafer, including an adapter board, a chip mounted on the adapter board, and a first plastic package layer covering the chip, through-silicon-vias are disposed on the adapter board, the first and second surfaces of the adapter board are respectively provided with external connection solder balls and/or external connection solder pads electrically connected with the through-silicon-vias. The process of manufacturing the package structure includes: after the first surface process of the adapter board is completed, bonding the first carrier on its first surface, then cutting the first carrier to expose the chip-mounting area, and then carrying out subsequent processes such as chip mounting, and finally cutting and removing the first carrier to complete the package.

Abstract: A method for cleaning a through via including the following steps is provided: heating a cleaning fluid to a predetermined temperature; mixing the cleaning liquid with an inert gas and entering into a cleaning cavity; atomizing the cleaning liquid in an atomizer to spray on a wafer surface and to wet an inner wall and a bottom of the through via; and closing a cleaning liquid valve.

Abstract: A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.

Abstract: The present invention relates to a millimeter wave radar component package, comprising: a box cover, having a metal layer arranged on inner surface of the box cover, the metal layer facing a channel of a box body, wherein a cavity is formed between the box cover and the box body; and the box body, comprising: a first insulator, connected with the box cover, wherein in the first insulator a channel is opened, and one end of the channel corresponds with the position of antenna and the other end is connected with the cavity; one or more chips, arranged on a second insulator in a flip manner and covered by the first insulator; the second insulator, arranged between the first insulator and a third insulator; the third insulator; and the antenna and conductive lines, arranged in the third insulator and connected with pads of the one or more chips through the second insulator, wherein the conductive lines are exposed from the third insulator for electrical contact.

Abstract: The present application discloses a fan-out packaging structure and a packaging method for a chip. The structure includes first and second chips with oppositely fitted bottoms; metal terminals distributed around the first chip, one side of the metal terminals being on a same plane with the front of the first chip; a lead connected between the front of the second chip and the other side of the metal terminal; a packaging layer for packaging the first chip, the second chip, the lead the metal terminals; and a lead-out layer disposed on a first surface of the packaging layer and electrically connected to one side of the metal terminals and/or the front of the first chip.

Abstract: A method for cleaning a through via including the following steps is provided: heating a cleaning fluid to a predetermined temperature; mixing the cleaning liquid with an inert gas and entering into a cleaning cavity; atomizing the cleaning liquid in an atomizer to spray on a wafer surface and to wet an inner wall and a bottom of the through via; and closing a cleaning liquid valve.

Abstract: An active optical adapter plate comprises a main body, the main body comprises at least a through hole and at least a photoelectric detection area, the through hole is disposed on an end face of the main body and configured to insert an optical fiber to provide an optical path for an emission light of a laser; the photoelectric detection area is disposed on the end face of the main body having the through hole, and comprises a photoelectric detector used for detecting a reflected light of the emission light of the laser and converting the detected reflected light into an electrical signal.

Abstract: A method for constructing an external circuit structure is provided. The method is applied to an inner circuit substrate, wherein, the method comprises: laminating a copper foil and a prepreg on the inner circuit substrate; wherein, the prepreg is laminated between the copper foil and the inner circuit substrate; drilling at least one blind via from the copper foil to reach the copper circuit of the inner circuit substrate; removing smear generated in the at least one blind via during the drilling process; corroding off the copper foil; electroless copper plating on the prepreg to form an electroless plating copper layer on the prepreg; wherein, during the electroless copper plating process, a swelling process without desmearing process is implemented.

Abstract: A method of manufacturing a fan out wafer level package comprises: preparing conductive projections on an upper surface of a chip; mounting the chip on a carrier with the upper surface of the chip facing upwards; plastic packaging the chip to form a plastic packaging body with tops of the conductive projections being disposed outside the plastic package body; and implementing a redistribution line processing on the plastic package body. With this method, chips can be made small and thin and the manufacturing processes can be simplified.

Abstract: A solution for dissipating heat generated from high power chip packages, e.g., a fcBGA package, wbBGA package, 2.5D/3D TSV package, PoP, etc. The heat dissipation system may include a high power chip package including a high power chip. A micro-jet may be attached to the high power chip. A micro-pump may be in fluidic communication with the micro-jet. A heat exchanger may be in fluidic communication with the micro-pump. The high power chip package is assembled on the same PCB with the micro-pump and the heat exchanger.

Abstract: An optical communication apparatus comprises a laser, a laser driver chip, a photodetector, an amplifier chip, an assembling plate and at least two I/O interfaces. The laser, the laser driver chip, the photodetector and the amplifier chip are disposed on the assembling plate. The laser is connected to the laser driver chip via transmission lines and the photodetector is connected to the amplifier chip via transmission lines. A plurality of conducting vias are formed in the assembling plate, the laser driver chip and the amplifier chip are respectively connected to different I/O interfaces via electrical transmission lines passing through the conducting vias. The laser is connected to an optical fiber to transmit optical signals, and the photodetector is connected to another optical fiber to receive optical signals. A method of assembling such an optical communication apparatus is also provided.

Abstract: A method for polishing a polymer surface is provided by an embodiment of the present invention. The method includes: curing the polymer surface; polishing the polymer surface cured through a CMP process. By using the method for polishing a polymer surface provided by embodiments of the present invention, the mentioned problems in the prior art are solved. The uniformity of the polymer surface can be improved to <1% through a CMP process, which can meet the requirements of high density and small linewidth integration.

Abstract: A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.

Abstract: A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.

Abstract: An optical fiber assembly and a method of assembly thereof. The optical fiber assembly includes a support plate defining an array of support plate through holes, and an alignment template plate defining an array of alignment template plate through holes. At least one support plate through hole or alignment template plate through hole may be flared. At least one support plate through hole or alignment template plate through hole may include a compliant film.

Abstract: A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Abstract: Techniques for fabricating fine-pitch micro-bumps are disclosed. According to one embodiment, a fabrication process may comprise the following steps: depositing a dielectric layer on a wafer; forming a pattern of through holes in the dielectric layer; depositing a seed metal layer on top of the dielectric layer and inside the through holes; depositing a layer of UBM metal on top of the seed metal layer (including inside the holes), and further filling the holes with a low melting point metal; performing chemical mechanical polishing (CMP) to remove conductive material(s) outside the holes and/or on the surface of the dielectric layer, such that the metal stacks of adjacent holes are insulated by the dielectric material between them; and etching the dielectric material surrounding the holes to cause the tip of the metal stacks to extend slightly higher than the surrounding dielectric surface, thereby forming fine-pitch micro-bumps.

Abstract: A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 ?m.

Abstract: A TSV wafer thinning controlling method and system is provided, which can improve the accuracy of the wafer thinning technique. The system includes a chuck table used for carrying a wafer and a grinding device used for thinning the wafer; and further includes: an infrared sensor equipped on the chuck table or grinding device, and a measurement feedback system connected with the infrared sensor and the grinding device; wherein, the infrared sensor comprises an infrared emitting and receiving circuit, signal amplifying and filtering circuit and a data processor.

Abstract: Techniques for fabricating fine-pitch micro-bumps are disclosed. According to one embodiment, a fabrication process may comprise the following steps: depositing a dielectric layer on a wafer; forming a pattern of through holes in the dielectric layer; depositing a seed metal layer on top of the dielectric layer and inside the through holes; depositing a layer of UBM metal on top of the seed metal layer (including inside the holes), and further filling the holes with a low melting point metal; performing chemical mechanical polishing (CMP) to remove conductive material(s) outside the holes and/or on the surface of the dielectric layer, such that the metal stacks of adjacent holes are insulated by the dielectric material between them; and etching the dielectric material surrounding the holes to cause the tip of the metal stacks to extend slightly higher than the surrounding dielectric surface, thereby forming fine-pitch micro-bumps.