Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.

Abstract: A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.

Abstract: An apparatus for receiving an asynchronous data signal may include a clock generator that generates a clock signal having a frequency approximately equal to the bit rate of the asynchronous data signal. An edge detector may detect transitions of the asynchronous data signal. A dead-band detector may detect when a transition of the clock signal used to sample the data signal occurs within a predetermined amount of time of a transition of the asynchronous data signal so that data sampled on that transition of the clock signal may be invalid. The phase of the clock signal may be adjusted if the transition of the clock signal occurs within this predetermined amount of time.

Abstract: A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register.

Abstract: A system and method for displaying and configuring parameters in a fieldbus configuration system. The fieldbus configuration utility first determines the devices and blocks present in the system, and then determines the parameters of each block. When the parameters are displayed, an object is displayed proximate to certain of the parameters. The object includes a color and/or shape which indicates the type or class of parameter. The user can also configure alarms and trends using the improved graphical interface of the present invention. The user configures alarms and trends by assembling a graphical program or wiring diagram on the screen which comprises a selected one or more block icons and an icon representing the device receiving the trend or alarm. The system also includes a periodic update window which is used to obtain periodically updated values of selected parameters.

Abstract: A system and method for reducing linearity errors in an A/D converter, such as a delta-sigma converter. The linearity errors in the delta-sigma converter are modeled by generating a set of digital signals representative of an inputted sine wave. The set of digital signals are low-pass filtered and subjected to a fast Fourier transform algorithm to generate a frequency domain representation of the sine wave. Thereafter, a net linearity error spectrum is removed from the frequency domain representation and inverse Fourier transform back into the time domain. The filtered set of digital signals are also sorted into subsets of digital signals where each signal in a subset corresponds to a particular output of a delta-sigma modulator contained within the delta-sigma converter. A fast Fourier transform algorithm is applied to each of the filtered subsets of digital signals to generate a frequency domain representation thereof.

Abstract: A graphical programming system and method which includes three-dimensional nodes that are wired or connected to from a graphical program or block diagram. Each of the three-dimensional nodes includes a plurality of sides that are designed to receive pre-defined inputs. In one embodiment, each node includes a left side for receiving data input and a right side for producing output data. The upper or top side of each node is designed to receive inputs regarding error conditions and/or initialization information. The front side of each node is reserved for displaying the name of the node or the function performed by the node. The back side of each node is reserved for timing and synchronization inputs. The bottom side of each node is designed to receive base configuration information and/or type declaration information. The user is only allowed to connect data of the specified type to the designated inputs of each node.

Abstract: A system and method for creating a fieldbus configuration on a computer system. The user assembles a graphical program or wiring diagram on the screen which comprises a selected plurality of function block icons which are linked with one or more wires connecting the function block icons. As the user assembles the fieldbus configuration wiring diagram, the system automatically creates and displays a schedule which visually presents the schedule being created. The schedule comprises one or more schedule bars for graphically or visually indicating the order of execution of the function blocks. The user can change the order of execution indicated by the schedule by graphically manipulating the schedule bars in the schedule. The user can also place one or more loop structures in the editor window which encapsulate a group of function block icons. The loop structure is used to specify a rate for the function block icons comprised within the loop structure.

Abstract: A software monitor utility is disclosed which capture and displays General Purpose Interface Bus (GPIB) calls made to GPIB driver software in real time. The GPIB driver software controls a GPIB interface. The GPIB interface is coupled to one or more GPIB instruments. The monitor utility is configured to record and display both the start and end time of a GPIB operation, where end time is the time control is returned to the GPIB application. In addition, for asynchronous GPIB calls, the monitor utility records and displays the end time of the corresponding asynchronous operation. Also, the monitor utility provides the option of substituting a monitor-enabled version of a key driver module for a non-enabled version upon entrance to the utility. Furthermore, an option of provided for restoration of the non-monitor-enabled version upon exit from the utility.