Abstract: A video capture system and method which includes improved software control of image acquisition and processing. The method comprises first creating an image application using one or more objects. Acquired data is preferably stored in an image object, and one or more objects, e.g., a viewer object or image processing object, are configured to share the image object, i.e., to dynamically bind to or communicate with the image object during program execution. When the application begins execution, the computer system acquires image data and stores the image data in an image object. A first object then dynamically binds to the image object, i.e., communicates with the image object, to access the image data contained in the image object and process the image data in response to the binding. This dynamic binding or communication, as well as the subsequent processing of the image data, occurs without user intervention.

Abstract: A system and method that reduces system cost in testing defective batteries. In a particular embodiment, a test system may be configured to reduce system cost by wiring two-wire relays from a plurality of batteries to a plurality of multiplexers located in a first stage. The number of two-wire relays is equal to: B/2+4.5 if B is odd B/2+5 if B is even where B is the number of batteries. The batteries may be associated with a particular combination of input channels of the multiplexers located in the first stage. The outputs of the multiplexers located in the first stage may then be connected to the inputs of at least one multiplexer located in a second stage. The outputs of the at least one multiplexer located in the second stage may then be connected to at least one instrument, such as a multimeter.

Abstract: A remote device access (RDA) feature for enabling access and control of remote devices in a data acquisition (DAQ) system. The data acquisition system comprises at least one client computer system executing a client DAQ application. The data acquisition system also comprises one or more server computer systems coupled to the client computer system through a network, wherein each server computer includes a data acquisition device which is controllable by the client DAQ application. The RDA method comprises the client DAQ application making a call to access the remote DAQ device in the server computer. In response to a determination that the call is intended for a remote DAQ device (the identical call could be intended for a local DAQ device), the call is then packaged into one or more packets and transferred to the server computer. The packets are preferably transferred using a remote procedure call (RPC).

Abstract: An analog to digital (A/D) converter system and method which provides improved resolution and reduced noise for integrating-type ADCs, including dual slope, multi slope, and sigma-delta type A/D converters. After the ramp-up interval of either a dual slope or multi slope integrating A/D converter, the ramp-down interval occurs, wherein a reference signal is then applied to the integrator to return the integrator to its original value. The clock cycles are counted while the reference voltage is applied to determine a primary slope count value. During the ramp-down interval, while the reference voltage is applied, two or more integrator voltages are measured. In one embodiment, a first integrator voltage is measured before the original value and a second integrator voltage is measured after the original value, e.g., before and after the zero crossing. The method then determines a fractional slope count based on the measured two or more integrator voltages, i.e.

Abstract: A system and method for generating source code example files for an application program in a computer system. In the preferred embodiment, the system and method is used for creating source code example files for the NI-DAQ driver software from National Instruments. The user first generates a code flow description file. The code flow description file is written in a code flow description language which is independent of a plurality of programming languages, i.e., which includes only common programming elements from the plurality of programming languages. The user then specifies one or more target programming languages. The present invention includes a Code Generator which generates one or more target example source code files in the specified target programming languages in response to the code flow description file.

Abstract: An electrical power supply is described which includes a floating current source. The floating current source includes a current source providing a selected amount of electrical current to a first terminal, and a current sink receiving the selected amount of electrical current from a second terminal. The current source is adapted for coupling to a first electrical voltage level which is positive with respect to a reference potential. The current sink is adapted for coupling to a second electrical voltage level which is negative with respect to the reference potential. The selected amount of current may be proportional to a reference current flowing through both the current source and the current sink. The current source and sink may each include a pair of transistors coupled together such that a flow of electrical current through one of the pair of transistors produces a proportional flow of electrical current through the other transistor.

Abstract: A system and method for calibrating an analog to digital (A/D) converter. The A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality of current generators, and wherein one or more of the current generators may produce linearity errors in the A/D converter. The A/D converter includes a switching element connected to the internal D/A converter. During calibration, the switching element operates to adjust connections to the current generators in the internal D/A converter one or more times according to different switching patterns, thereby causing different ones of the current generators to be stimulated by an input to the A/D converter. This avoids the necessity of using a complex and costly waveform generator input during calibration, which would normally be required to ensure that all of the current generators in the internal D/A converter are stimulated. Rather, a much simpler input can be used in calibrating the A/D converter, thereby reducing cost.

Abstract: A system and method for performing pattern matching to locate zero or more instances of a template image in a target image. The method first comprises sampling the template image using a Low Discrepancy sequence, also referred to as a quasi-random sequence, to determine a plurality of sample pixels in the template image which accurately characterize the template image. The Low Discrepancy sequence is designed to produce sample points which maximally avoid each other. After the template image is sampled or characterized, the method then performs pattern matching using the sample pixels and the target image to determine zero or more locations of the template image in the target image. The method may also perform a local stability analysis around at least a subset of the sample pixels to determine a lesser third number of sample pixels which have a desired degree of stability, and then perform pattern matching using the third plurality of sample pixels.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: A system and method for controlling an instrumentation system, wherein the present invention includes an improved instrument driver software architecture. The instrument driver software architecture of the present invention provides a number of features, including instrument interchangeability, i.e., the use of interchangeable virtual instruments or interchangeable instrument drivers, improved performance, an improved attribute model, improved range checking, and improved simulation features, among others.

Abstract: A system and method for performing pattern matching to locate zero or more instances of a template image in a target image. The method first comprises sampling the template image using a Low Discrepancy sequence, also referred to as a quasi-random sequence, to determine a plurality of sample pixels in the template image which accurately characterize the template image. The Low Discrepancy sequence is designed to produce sample points which maximally avoid each other. After the template image is sampled or characterized, the method then performs pattern matching using the sample pixels and the target image to determine zero or more locations of the template image in the target image. The method may also perform a local stability analysis around at least a subset of the sample pixels to determine a lesser third number of sample pixels which have a desired degree of stability, and then perform pattern matching using the third plurality of sample pixels.

Abstract: A system and method for performing pattern matching to locate zero or more instances of a template image in a target image. The method first comprises sampling the template image using a Low Discrepancy sequence, also referred to as a quasi-random sequence, to determine a plurality of sample pixels in the template image which accurately characterize the template image. The Low Discrepancy sequence is designed to produce sample points which maximally avoid each other. After the template image is sampled or characterized, the method then performs pattern matching using the sample pixels and the target image to determine zero or more locations of the template image in the target image. The method may also perform a local stability analysis around at least a subset of the sample pixels to determine a lesser third number of sample pixels which have a desired degree of stability, and then perform pattern matching using the third plurality of sample pixels.

Abstract: A system and method for configuring an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. A graphical program is first created, wherein the graphical program implements a measurement function. The graphical program may include a front panel and a block diagram. The method then generates a hardware description based on at least a portion of the graphical program. The hardware description describes a hardware implementation of the at least a portion of the graphical program. The method then configures the programmable hardware element in the instrument utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the at least a portion of the graphical program. The instrument then acquires a signal from an external source, and the programmable hardware element in the instrument executes to perform the measurement function on the signal.

Abstract: Analog-to-digital conversion with reduce sparkle codes. An analog-to-digital converter includes a plurality of comparators each coupled to receive an analog input signal, and an adder decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective reference signal for comparison with the analog input signal. Each comparator outputs a digital value indicative of the comparison between the analog input signal and the respective reference signal. The adder decoder adds the digital output signals generated by the comparators and outputs a digital representation of the analog input signal based on the result. This system may advantageously provide for a more efficient way to convert analog signals to digital signals without the generation of sparkle codes. The adder decoder may be a pyramid of adders. A sigma-delta converter may include the comparators in the analog-to-digital portion in the feedback loop and the adder decoder outside of the feedback loop.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: A computer-based virtual instrumentation system including a host computer and an embedded system or device, wherein graphical programs created using the computer system can be downloaded to the embedded system for execution in a real-time or more deterministic manner. The present invention thus provides a method for automatically generating an embedded application in response to a graphical program created by a user. This provides the user the ability to develop or define instrument functionality using graphical programming techniques, while enabling the resulting program to operate in an embedded real-time system. The invention includes a novel method for configuring the embedded system. During execution of a graphical program in the embedded system, the block diagram portion executes in the embedded system, and the host CPU executes front panel display code to display on the screen the graphical front panel of the graphical program.

Abstract: A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register.

Abstract: An improved data acquisition system for digitizing and storing analog data at a selectable sample rate. The analog data signal is first digitized at a rate defined by a high-frequency clock signal. A decelerator collects every N digital data samples and outputs the samples to N memory partitions at a reduced rate equal to the original clock frequency divided by N. The N memory partitions are further configured to receive N store-enable signals corresponding to each of the N digital data samples. Each of the N store-enable signals determines whether a memory partition will store the corresponding digital data sample. By choosing an appropriate pattern for the N store-enable signals, only a portion of the generated digital data signals is stored in memory. This results in a selectable effective sampling rate for the analog data.

Abstract: A system and method for dynamically re-programming the acquisition cycle of a video acquisition system. The video acquisition system comprises a host computer and a video source. The host computer comprises a CPU, a system memory, and a video capture board. The video capture board receives a video signal from the video source. The video signal comprises a sequence of frames. The video capture board includes a DMA Controller which writes video frames to system memory under the control of a circularly linked list of commands. The linked list contains a plurality of sublists, each of which schedules the DMA transfer of a video frame to a corresponding video buffer in system memory. By removing a sublist from the linked list, a video buffer is removed from the set of buffers targeted for data transfer by the DMA Controller. By adding a sublist to the linked list, a video buffer is restored to the targeted set.