Abstract: Disclosed is a method for producing a transgenic angiosperm plant, particularly a monocot, comprising the step of transforming an immature embryo of an angiosperm plant with a DNA fragment expressible in said angiosperm embryo, said DNA fragment comprising a promoter region derived from an &agr;-amylase gene of a plant, and an exogenous gene encoding a desired gene product, said promoter region being inducible under a sugar-depleted or sugar-free condition to promote the expression of said gene, whereby at least a part of the resultant transgenic angiosperm plant has the ability to express said gene product. Transgenic angiosperm plants and transgenic angiosperm plant seeds are also disclosed. The transgenic angiosperm plant seeds may have application in the industrial production of alcohol, beer, glucose and the like.

Abstract: The present invention is directed to a method for the production of a transgenic plant of rice crop comprising the steps of infecting an immature embryo of rice crop with the genus Agrobacterium for transformation; co-culturing the infected embryo with a dicot suspension culture during the step of transformation; allowing the transformed embryo to grow into a callus in a selective medium comprising a sufficient amount of a plant growth hormone for the growth of rice crop; and allowing the cultured callus to regenerate root and shoot in a regeneration medium comprising a pre-determined amount of nutrients for the growth of rice crop. The invention is further directed to a transformed rice plant made by methods of this invention.

Abstract: Disclosed is a new, effective and general methodology to prevent viral infection, which methodology is divided into two parts: 1) induction of the apoptosis (programmed cell death) of a host upon viral infection to block viral reproduction; and 2) the use of an apoptosis triggering gene, the persistency-associated gene 1 (pag1, now renamed as hem1 in light of the position thereof in the restriction map of the Hz-1 viral genome) to prevent the viral infection.

Abstract: A process is provided for producing a bioceramic composite in which an alumina based ceramic substrate is coated with an intermediate calcium pyrophosphate layer to cement a porous calcium phosphate material to the alumina based ceramic substrate. In one aspect of the invention, the porous calcium phosphate material is a porous lattice made from natural bone. A bioceramic composite which includes an alumina-based ceramic substrate, an intermediate calcium pyrophosphate layer and a porous natural bone material bonded to the intermediate calcium pyrophosphate layer is also disclosed.

Abstract: A charge pumping circuit includes a plurality of cascaded voltage gain circuit stages. Each circuit stage has an switching transistor with a source connected electrically to a drain of the transistor of an immediately succeeding one of the circuit stages, and a gate connected electrically to the source of the transistor of the immediately succeeding one of the circuit stages, and a capacitor. The capacitor of odd ones of the circuit stages is connected electrically across a first clock and the source of the transistor of the respective circuit stage. The capacitor of even ones of the circuit stages is connected electrically across a second clock, which is out of phase with the first clock, and the source of the transistor of the respective circuit stage.

Abstract: A full-search block matching motion estimation processor includes a memory management unit for buffering search data of a (2P+N).times.(2P+N) search area, and a processor element array unit. The search area is divided into rows of the search data, and the memory management unit has N output bus lines and sequentially outputs the rows of the search data at the output bus lines. The processor element array unit includes an array of processor elements, each of which has at least one reference data input, at least one search data input connected to one of the search data inputs of the processor elements on the same row of the array and further connected to one of the output bus lines of the memory management unit, a partial sum output, and a partial sum input connected to the partial sum output of a preceding one of the processor elements on the same row of the array.

Abstract: The present invention is directed to a method for producing a gene product by expressing a gene encoding the gene product in angiosperm host cells, comprising the steps of constructing a vector expressible in angiosperm host cells, the vector comprising a promoter region derived from an .alpha.-amylase gene of a plant, and a gene encoding a desired gene product; transforming a compatible angiosperm host cell with the vector; cultivating the resultant transformant host cell; subjecting the cultivated transformant host cell to a sugar-depleted or sugar-free condition to promote the expression of the gene under the control of the promoter region; and recovering the expressed gene product.

Abstract: A method for generating r-bit parallel CRC code for a data source grouped into at least one successive p-bit parallel data group and a q-bit parallel data group is disclosed. The number q is less than the number p.

Abstract: An address generator includes an up/down counter driven by a clock to generate a varying output, an increment counter driven by the clock to generate an incrementing output, and a comparator comparing the varying output and the incrementing output and generating a comparing output. A first register is used for storing an initial address therein. A second register is capable of storing a plurality of step size values therein. The second register is connected electrically to the comparator to receive the comparing output and to the up/down counter to receive a least significant bit of the varying output. The second register outputs one of the step size values according to combination of the comparing output and the least significant bit of the varying output. An adder is connected electrically to the registers and generates a new address equal to a sum of the initial address and one of the step size values.

Abstract: A polishing tool includes a tool body and a polishing member which is mounted rotatably on the tool body and which has a central hole unit formed through the polishing member. The working surface of the polishing member has a plurality radially extending slots which are spaced apart from each other in an angularly equidistant relation and which extend from the inner periphery of the working surface to the outer periphery of the working surface. A plurality of flat working surface sections are defined on the working surface of the polishing member by the slots. When a slurry consisting of a lubricating liquid and abrasive grains flows onto the working surface of the polishing member via the central hole unit and when the polishing member is rotated on the tool body, each of the abrasive grains moves across all of the slots and from the inner periphery of the working surface to the outer periphery of the working surface, by hydrodynamic effect, so as to polish positively and effectively the workpiece.

Abstract: An IEEE Std. 1149.1 boundary scan circuit which is capable of performing built-in self-testing includes a logic circuit, cascaded input boundary-scan cells that form an input boundary-scan register connected to input nodes of the logic circuit, cascaded output boundary-scan cells that form an output boundary-scan register connected to output nodes of the logic circuit, and a test access port system for controlling operation of the input and output boundary-scan cells. The test access port system provides a built-in self-test control signal to the input and output boundary-scan cells when executing built-in self-testing. The input boundary-scan register is reconfigurable to operate as a test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal.

Abstract: In a method for producing a semiconductor device using a logic simulation approach, a circuit model for a user-specified design of a multi-peak resonant tunneling diode-based electronic circuit is provided and includes a plurality of circuit devices. One of the circuit devices is a multi-peak resonant tunneling diode which is modeled by a parasitic resistance in series with parallel combination of a voltage-controlled current source and an intrinsic capacitance. The voltage-controlled current source has an equivalent circuit model with a function stage for realizing current-voltage characteristic curve of the resonant tunneling diode. The function stage includes parallel combination of at least one first circuit branch, at least one second circuit branch and a third circuit branch. Each of the first and second circuit branches has a resistor, a diode and a voltage source. The third circuit branch has a resistor and a voltage source.

Abstract: A method for producing fine silver-palladium alloy powder includes the steps of: (A) preparing separately a silver nitrate solution and a palladium nitrate solution and mixing the solutions, and then adding a neutralizing and complexing agent to the mixed solutions to adjust the pH thereof to about 2.5-3.5, whereby a first mixture containing silver and palladium ions is obtained; (B) preparing a second mixture containing a reductant and a surfactant; (C) bringing the first mixture into contact with the second mixture at a reaction temperature of 15.degree.-50.degree. C. under stirring in order to permit the silver and palladium ions to be reduced and to coprecipitate so as to form silver-palladium alloy particles; and (D) recovering the coprecipitated silver-palladium alloy particles, thereby obtaining the fine silver-palladium alloy powder.

Abstract: A vector summation device includes a squaring circuit for receiving a number of input voltage signals, and a square-root circuit having first and second current terminals connected electrically to the squaring unit. The squaring circuit receives first and second current signals respectively from the first and second current terminals of the square-root circuit. The difference between the current values of the first and second current signals is proportional to the sum of the squares of the voltage values of the input voltage signals. The square-root circuit generates an output voltage signal with a voltage value that is proportional to the square-root of the difference between the current values of the first and second current signals.

Abstract: A variable frequency oscillator which can be implemented entirely in a semiconductor chip, which is variable over a broad frequency range and which has relatively low phase noise, includes a variable impedance circuit, a reactive load connected to an output terminal pair of the variable impedance circuit, and a negative impedance circuit having an output terminal pair connected to the output terminal pair of the variable impedance circuit. In one embodiment, the negative impedance circuit has an input terminal pair connected to an input terminal pair of the variable impedance circuit to serve as a positive feedback path for the variable impedance circuit. In another embodiment, the negative impedance circuit includes a pair of level shifters which ensure that the variable impedance circuit is properly biased and works in a forward active region.

Abstract: A variable impedance circuit includes a differential circuit, an impedance element, a variable current attenuator and a pair of level shifters. The differential circuit includes a transistor pair with a pair of input terminals, a pair of output terminals, and a pair of emitters. The impedance element is connected between the emitters of the transistor pair. The variable current attenuator has a pair of input terminals connected respectively to the output terminals of the transistor pair, a pair of output terminals, and a pair of control inputs for receiving a control voltage to vary the current gain of the variable current attenuator. Each of the level shifters has an input terminal connected to a respective one of the output terminals of the variable current attenuator, and an output terminal connected to a respective one of the input terminals of the transistor pair. The level shifters ensure that the transistor pair and the variable current attenuator are properly biased.