Abstract: A receiver (22) includes an IF filter (44) and a nearby process-variant circuit (80) formed on a common semiconductor substrate (24). The actual center frequency of the IF filter (44) is determined by resistors (70, 74) and capacitors (72, 76) exhibiting imprecise values and is unlikely to equal a nominal center frequency. The process-variant circuit (80) includes a test resistor (102) and test capacitor (104) formed using the same resistor-forming and capacitor-forming processes used to form the IF filter resistors (70, 74) and capacitors (72, 76). In response a test signal (88) from the process-variant circuit (80) and a reference signal (84) from a process-invariant circuit (82), a tuning parameter for a tunable local oscillator (90) is determined so that a local oscillation signal (94) will exhibit a frequency which, when mixed with an RF signal (38) yields an IF signal (42) at the actual center frequency of the IF filter (44).

Abstract: A lithographic mask for use in an off-axis illumination system is provided. The mask includes a transparent substrate and a first patterned layer of an opaque material proximate to a first side of the transparent substrate. A second patterned layer is formed over the first patterned layer. The second patterned layer comprising a dielectric material configured to phase shift an exposure energy directed towards the mask. Over the second patterned layer a third patterned layer is formed. The third patterned layer is manufactured from an opaque material.

Abstract: An integrated RF power amplifier 20 includes an on-chip input transformer (24) and an on-chip output transformer (28). Each of the transformers (24, 28) is formed from four spirals. Each primary winding (34, 42) and each secondary winding (38, 44) includes positive and negative spirals arranged so that positive current rotates in opposing rotational directions in the positive and negative spirals. The secondary winding (38) of the input transformer (24) and the primary winding (42) of the output transformer (28) each has a center tap (48, 50) located at the electrical and physical center of the winding. Positive and negative amplifiers (26) couple between the secondary winding of the input transformer (24) and the primary winding of the output transformer (28). DC biasing for the amplifiers (26) is provided through the positive and negative spirals of the center-tapped windings (38, 42) from the respective center taps (48, 50).

Abstract: A heterojunction bipolar transistor (20, 60) is provided with a silicon (Si) base region (34, 74) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36, 72) proximate the base region (34, 74) and a distal gallium phosphide (GaP) emitter layer (40, 66). The GaAs emitter layer (36, 72) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region (70) which serves as the emitter and a non-doped region (68) on which the intrinsic portion of the transistor (60) is formed.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor. The tunnel diode (32) may be formed at a junction between a mono-crystalline silicon layer (88) at a region (98, 100) which also serves as a source or drain of a transistor (36, 54) and a poly-crystalline silicon layer (106). The poly-crystalline silicon layer (106) also serves as a non-metallic, conductive interconnection (55) to save space.