Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.

Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.

Abstract: A method is disclosed, including positioning a lead wire of a gate chip at a distance of less than 10 nm from a semiconductor heterostructure. The heterostructure includes a surface layer and a subsurface layer. The method also includes inducing an electrostatic potential in the subsurface layer by applying a voltage to the lead wire. The method also includes loading a charge carrier into the subsurface layer. The method also includes detecting the charge carrier in the subsurface layer of the semiconductor heterostructure by emitting a radio-frequency pulse using a resonator coupled to the at least one lead wire of the gate chip, detecting a reflected pulse of the emitted radio-frequency pulse, and determining a phase shift of the reflected pulse relative to the emitted radio-frequency pulse. The method also includes characterizing the quantum dot by measuring valley splitting of the quantum dot.

Abstract: An antenna is disclosed, including an omnidirectional antenna with a first conical antenna section. The omnidirectional antenna forms a first feed aperture. The omnidirectional antenna forms a field of view aperture in a wall of the omnidirectional antenna. The antenna also includes a directional antenna, disposed within an interior portion of the omnidirectional antenna such that the directional antenna has an electrically unobstructed field of view through the field of view aperture in the wall of the omnidirectional antenna. The antenna also includes a feed cable, electrically coupled to the directional antenna and disposed within the omnidirectional antenna and the first feed aperture.

Abstract: A method of transmitting a message includes, for each data block, generating a root matrix using a generator, generating a quasi-cyclic matrix H using the root matrix, encoding the block using H to create a codeword, and transmitting the codeword. The root matrix includes three submatrices: an identity matrix in an upper-left-hand portion of the root matrix, an identity matrix in a lower-left-hand portion of the root matrix, and a circulant matrix in a right-hand portion of the root matrix. The circulant matrix equals the sum of an identity matrix and an identity matrix with rows shifted once to the right. Generating H includes expanding the root matrix by replacing 0 elements in the root matrix by a square matrix of 0 elements and replacing 1 elements in the root matrix by a shifted diagonal matrix. Non-zero elements of the diagonal matrix are selected from GF(q) based on the generator.

Abstract: A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.

Abstract: A scanning tunneling microscopy based potentiometry system and method for the measurements of the local surface electric potential is presented. A voltage compensation circuit based on this potentiometry system and method is developed and employed to maintain a desired tunneling voltage independent of the bias current flow through the film. The application of this potentiometry system and method to the local sensing of the spin Hall effect is outlined herein, along with the experimental results obtained.

Abstract: A device for securing a door includes an elongated flat rigid member. A first segment is connected to a second segment by a transition segment perpendicular to the first and second segments. The first segment forms an aperture to admit a restraining device. The device also includes a first blocking member having two apertures and configured to engage the first member such that the restraining device restrains the first blocking member relative to the flat rigid member. The device also includes a second blocking member configured to lockably engage the second segment, thereby securing the device relative to a frame of the door with the first and second segments on opposite sides of the frame. When the device is secured and the door closed, and the first blocking member restrained relative to the flat rigid member, the door is blocked from being opened by the first and second blocking members.

Abstract: A CNOT gate includes a clock line, splitter, and first and second store-and-launch gates (SNLs) to each output a fluxon in accordance with a clock fluxon and polarities of an input fluxon and the clock fluxon. The CNOT gate also includes first and second IDSN gates. When one fluxon input is received, the IDSN gate outputs one fluxon in accordance with a polarity of the fluxon input. When two fluxon inputs are received, the IDSN gate outputs two fluxons in accordance with an inverse polarity of the fluxon inputs. The CNOT gate also includes first and second NOT gates to receive a fluxon output from the first IDSN gate and output a fluxon of opposite polarity, and a third NOT gate to receive a fluxon output from the second IDSN gate and output a fluxon of opposite polarity.

Abstract: An always-on, exchange-only (AEON) qubit is comprised of three two-level systems (e.g., semiconductor quantum dot or other spin encoded qubit) and can be operated at a “sweet spot” during both single qubit and two-qubit gate operations. The “sweet spot” operation is immune to variations in noise with respect to nontrivial detuning parameters defining the AEON. By operating at the “sweet spot,” both single and two-qubit gate operations can be performed using only exchange pulses (e.g., DC voltage pulses applied to tunneling gates).

Abstract: An always-on, exchange-only (AEON) qubit is comprised of three two-level systems (e.g., semiconductor quantum dot or other spin encoded qubit) and can be operated at a “sweet spot” during both single qubit and two-qubit gate operations. The “sweet spot” operation is immune to variations in noise with respect to nontrivial detuning parameters defining the AEON. By operating at the “sweet spot,” both single and two-qubit gate operations can be performed using only exchange pulses (e.g., DC voltage pulses applied to tunneling gates).

Abstract: A method is disclosed for using digital camera fingerprints to create bins of digital images generated by the same digital camera. The method includes determining, for each digital image in the set of digital images, a digital fingerprint. The method also includes sorting each digital image into one of a high-quality subset and a low-quality subset. The method also includes sorting each digital image in the high-quality subset into one of a plurality of bins. In each bin the images were determined, based on the digital fingerprints of the images in the bin, to have been generated by a single digital camera associated with the bin. The method also includes sorting each digital image in the low-quality subset into one of the plurality of bins, the sorting being performed based on the digital fingerprint of the digital image.

Abstract: A multi-user access control device provides controlled access to a sensitive system by enabling/disabling an input/output port in communication with said sensitive system. Tokens are held by users and provide for confirmation of group membership and authentication. Upon authentication of the users, an enable signal is provided to a relay providing power to an external port. The external port may provide power to an input/output device allowing the user to interact with the sensitive system. The external port may provide power to a network port of the access control device allowing for management of the access control device or allowing for auditing of the access control device.

Abstract: Superconducting regions formed with a crystal provide highly doped regions of acceptor atoms. These superconducting regions are used to provide superconducting devices wherein non-epitaxial interfaces have been eliminated. A method is provided to highly doped regions of a crystal to form the superconducting regions and devices. By forming the superconducting regions within the crystal non-epitaxial interfaces are eliminated.

Abstract: A method is disclosed for calibrating a deposition rate in an aerosol jet printer. The method includes providing a substrate defining an array of wells, each defining a volume. The method also includes defining a toolpath such that a dispensing nozzle passes over the wells. The method also includes defining a dwell time such that the nozzle remains centered above each well for an amount of time equal to the dwell time, after which the nozzle follows the toolpath to be centered over the following well. The dwell time defines a deposition rate based on the volume of the wells. The method also includes causing the nozzle to move along the toolpath, depositing material into the wells. The method also includes observing one of overfilling and underfilling and adjusting dispensing parameters to effect a modified deposition rate, until the wells are being filled to within a tolerance of exactly full.

Abstract: A method is disclosed for pairwise combination of data elements of an input data stream. Steps are performed for each data element. A master controller reads the data from the stream and increments a counter. A register is instantiated, holding at least two words of memory and corresponding to the counter, by updating a register map and sending a message to a target processor via a logical pathway. The message instructs the target processor to create the register in local memory, including first and second memory locations, and an index corresponding to a value i. The target processor copies the data into the first memory location. For every other register corresponding to a value less than i, the other register copies the data into the second memory location and outputs a unique pair, constructed from the data elements stored at the first and second memory locations, to a database.

Abstract: A method is presented for ranking documents identified in a search relative to a keyword. The method utilizes a set of training documents to provide a co-occurrence matrix and a transition matrix. A word pair relevancy measure is calculated for each word of the document to be ranked. These word pair relevancy measures are based upon the co-occurrence and transition matrices obtained from the training set and are utilized to calculate a document relevance measure. Documents identified in a search are ranked utilizing the document relevance measure.

Abstract: The present invention discloses a method for comparing a camera fingerprint to a query fingerprint. An estimate of a camera fingerprint is obtained from a set of one or more images, and the query fingerprint is obtained from one or more images. Using these values, normalized cross-correlations values are determined for each possible alignment of the two fingerprints. Prior to calculating the noise floor, a set including the highest normalized cross-correlation values is identified. A universal noise floor is then calculated excluding this set from the noise floor calculation. The universal noise floor is utilized in calculating a correlation energy for each possible shift. The correlation energy values are then examined to determine whether the camera fingerprint and the query fingerprint match. A visualization tool may also be used to compare the camera fingerprint and the query fingerprint and determine whether the camera fingerprint and the query fingerprint match.

Abstract: A method of fabricating a semiconductor capacitor is disclosed. The method includes forming a first trench in a semiconductor substrate, forming a dielectric lining layer in the first trench, and depositing a first capacitor conductor plate layer on the dielectric lining layer. The method also includes forming a second trench such that the dielectric lining layer is exposed. The method also includes forming a third trench such that the dielectric lining layer is exposed within the third trench. The method also includes depositing a second capacitor conductor plate layer in the second trench and depositing a third capacitor conductor plate layer in the third trench. The method also includes forming a first electrical contact between the first capacitor conductor plate layer and the second capacitor conductor plate layer and forming a second electrical contact between the first capacitor conductor plate layer and the third capacitor conductor plate layer.

Abstract: A method includes receiving, at a master controller, a matrix representing a graph and a first vector, and initializing a counter variable and an array to track dimensionality reduction for the matrix. The method also includes multiplying a subset of the matrix based on the counter variable, by a subset of the first binary vector based on the counter variable. Multiplying includes providing, the vector and a matrix portion to a first processor, and the vector and another portion of the matrix to a second processor. The method also includes, at the processors, multiplying the vectors by the portions of the matrix and returning the results. The method also includes combining the results at the master controller. The method also includes incrementing the counter variable and updating the tracking array for larger dimensionality reduction of the matrix. The method also includes constructing the logical pathway based on the tracking array.