Abstract: A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.

Abstract: A liquid crystal on silicon (LCOS) display pixel with dual storage capacitors for increasing the storage capacitance of the charge storage node for the liquid crystal pixel. The two capacitors are in a stacked arrangement. The bottom capacitor is formed by using a buried diffusion layer as the bottom electrode, a first layer of polysilicon (poly) as the top electrode and silicon dioxide as the dielectric. The top capacitor is a poly-to-poly capacitor formed by using the first layer of poly as the bottom electrode and a second layer of poly as the top electrode.