Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract: The invention relates to the field of signal processing. It is an object of the invention to provide for limitation of a signal voltage to a predetermined maximum voltage (Vmax). To this end, an input signal (Vin) is applied to a voltage divider which includes a variable-resistance component (T1) whose resistance is controlled by a control signal. An output signal (Vin?) is picked-up at the variable-resistance component (T1). The control signal is generated as an amplified difference between the output signal (Vin?) and a fixed reference voltage (Vmax/2), so that for an “overvoltage case” in which the value of the input signal (Vin) exceeds that of a predetermined maximum voltage (Vmax) the output signal (Vin?) is kept substantially constant.

Abstract: The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).

Abstract: The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used.

Abstract: The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT).

Abstract: The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s1, s2, s1*, s2*) is supplied.

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract: An amplifier is described which amplifies an input signal according to a defined amplification factor, and which generates an output signal. To reduce an offset fraction of the output signal the amplifier comprises a feedback path which has lowpass characteristics and which returns the output signal in a lowpass-filtered state to an input of the amplifier. The feedback path comprises an amplifier stage as well as at least one Miller capacitance connected between an input and an output of the amplifier stage.

Abstract: It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp?Voutn) with a stable common mode potential (½×(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path (24, 26, 30, 28, 36, 38, 34, 32) feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T1-T4), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path (24, 26, 30, 28, 36, 38, 34, 32) any coupling between separate control loops is avoided.

Abstract: The invention concerns a controllable current source or “charge pump” (12) in an integrated circuit, comprising two supply terminals (K1, K2) for the application of two supply potentials (V1, V2) as well as an output terminal (Kout) for the delivery of an output current, connected via a first controllable current path (T1) with the first supply terminal (K1), and via a second controllable current path (T2) with the second supply terminal (K2). In order to improve the current source (12) with regard to the quality of the output signal, it is provided according to the invention that the controllable current source (12) furthermore has a replica (T1?, T2?) of the current paths (T1, T2) in their non-controlled state, of which a replica output terminal (Kout?) is connected via a current mirror (T5 to T8) with the output terminal (Kout).

Abstract: The invention relates to an amplifier circuit comprising supply terminals (12, 14) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal (12) via a first biased transistor (P1a, P1b), a first node (K1a, K1b), an input transistor (Q1a, Q1b), a second node (K2a, K2b) and a second biased transistor (N1a, N1b) to the second supply terminal (14), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K2a, K2a) forms a pick-up in a resistor chain (R2a, R1, R2b), at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R2a, R1, R2b) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q1a, Q1b) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P3a, N3a, P3

Abstract: The present invention relates to the field of signal processing. It is an object of the invention to provide a circuit arrangement (VL) and a method for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, by means of which circuit arrangement and method it becomes possible to reduce signal interference. It is provided a voltage comparison (OPAMP2) within a closed-loop control of an output signal (Vin?), by means of which closed-loop control the value of said output signal (Vin?) is limited to a maximum value (Vmax/2). Thus, it becomes possible to prevent the generation of signal interference during signal processing. The voltage limiting method according to the invention uses as a reference quantity a reference voltage (Vmax/2) to which the output signal (Vin?) is compared in the context of closed-loop control.

Abstract: The invention relates to an integrated circuit arrangement (10) comprising at least one digital-analogue converter (12) with a multitude of current-source transistors (N1-N8) arranged parallel to each other for providing current components (I1-I8) that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors (N1-N8) can be subjected to a shared adjustment potential by way of an adjustment potential line (14), which adjustment potential defines the individual current components (I1-I8), and comprising an adjustment circuit (16) for providing the adjustment potential at the adjustment potential line (14). In order to drastically reduce interference, in particular noise, in the individual current components (I1-I8), the integrated circuit arrangement (10) comprises an external connection (18), which is connected to the adjustment potential line (14) for connecting an external capacitor (C0).

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). The circuit amplification (Vout/Vin) may be changed by selectively connecting or disconnecting impedances (R1, . . . RN). Integration elements (INT1. . . INT N) connected upstream from each of the control inputs of transistors (S1, . . . SN) used for this purpose ensure a certain temporal smoothing of the curve of the circuit amplification (Vout/Vin) when connecting or disconnecting an impedance (R1, . . . RN). The integration element particularly ensures that even in the event of a sudden change of the affected activation signal (VD1, . . . VDN), the affected impedance (R1, . . . RN) is not also suddenly disconnected or connected.

Abstract: The present invention relates to a circuit configuration having a feedback operational amplifier (AMP), which is implemented as fully differential, for amplifying an input signal differentially input to the circuit configuration and for outputting the amplified input signal as a differential output signal. In order to increase the freedom in setting the input common mode voltage, according to the present invention, a combination made of a coupling resistor (R1b) and a level shifter (I1b, Nsfb) connecting the positive amplifier output (y1) to the inverting amplifier input (x2) and a combination made of a coupling resistor (R1a) and a level shifter (I1a, Nsfa) connecting the negative amplifier output (y2) to the noninverting amplifier input (x1) are provided.

Abstract: A continuous-time delta-sigma analog digital converter for converting an analog input signal to a digital output signal, comprising an analog filter with at least one integration capacitor, a cycled quantifier which quantifies the filtered analog signal for generating the digital output signal, and a feedback device with at least one digital analog converter, which supplies at least a first analog feedback signal to the analog filter corresponding to the value of the digital output signal. The feedback device for generating a second feedback signal corresponding to the differentiated output signal of the quantifier, comprises a switching device coupled capacitively to the integration capacitor, by means of which device corresponding charge portions are transmitted to the integration capacitor when there is a variation in the digital output signal.

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20).

Abstract: The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). In order to be able to change the circuit amplification (Vout/Vin) easily and reliably in the circuit configuration (10) and simultaneously keep an impairment of the output signal (Vout) caused by noise relatively low, capacitance values (Cb, C) of the coupling path (12) and of the feedback path (14) are adjusted simultaneously to one another correlated in a special way.

Abstract: The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantizer, which quantizes the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal.