Patents Assigned to National Semiconductor, Inc.
  • Patent number: 7209528
    Abstract: Disclosed is a sampling circuit for a receiver in a wireless communication device that eliminates the need for separate discrete filtering components that can be expensive and bulky. The system utilizes techniques for ensuring that system components do not become saturated by blocker signals as a result of the removal of the discrete filter. Further, active filters are used in place of the discrete filter only when a blocker signal is present to minimize power consumption. In addition, the dynamic range of a sampling circuit can be altered in the presence of a blocker signal to ensure that the baseband signal is adequately detected.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: April 24, 2007
    Assignee: National Semiconductor, Inc.
    Inventor: James S. Prater
  • Patent number: 6408511
    Abstract: A method for providing an enhanced ball grid array attachment in low-temperature co-fired ceramic (LTCC) substrate is provided. A termination cup is formed in a substrate. The termination cup has a bottom formed by a termination pad over a via in a first tape layer and side walls formed by termination sides formed over side walls of a via in a second tape layer. A diffusion layer is formed over the termination cup. The diffusion layer helps to reduce the oxidation of the termination cup and to provide greater mechanical attachment strength. An electrically conductive adhesive may be used to connect a solder ball to the diffusion layer. Reflow then is used to complete the solder ball connection process.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: June 25, 2002
    Assignee: National Semiconductor, Inc.
    Inventor: Shaul Branchevsky
  • Publication number: 20010008479
    Abstract: An apparatus and method for creating multi-layer embedded ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates. In order to create multiple layers of electrodes, the individual electrode layers must be connected electrically. According to the present invention, a multi-layer capacitor is formed on a first ceramic tape layer. A second tape layer having an opening is placed on top of the first layer. The opening in the second layer is formed such that exposed vias are present on at least two sides of the opening to electrically connect to the electrodes. When the tape layers are pressed and fired, the exposed vias and electrodes form common electrical connections. A third layer having a terminal via may be placed on top of the second layer.
    Type: Application
    Filed: February 16, 2001
    Publication date: July 19, 2001
    Applicant: National Semiconductor, Inc.
    Inventor: Shaul Branchevsky
  • Patent number: 5796586
    Abstract: Discloses is a method for making substrate boards for use in packaging semiconductor devices. The substrate board has a plurality of conductive traces patterned on at least one side, and an anti-adhesive solder mask is applied over and around conductive traces lying at an outer portion of the substrate board. The center portion of the substrate board will therefore remain uncovered by the anti-adhesive solder mask material. As a result, the uncovered center portion of the substrate board and conductive traces provide a surface area that is substantially more adhesive than the outer portion covered with the anti-adhesive solder mask.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: August 18, 1998
    Assignee: National Semiconductor, Inc.
    Inventors: Shaw Wei Lee, Poh Ling Lee, Anthony E. Panczak
  • Patent number: 5453389
    Abstract: A method for manufacturing bipolar semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: September 26, 1995
    Assignee: National Semiconductor, Inc.
    Inventors: Robert J. Strain, Sheldon Aronowitz