Patents Assigned to NATIONAL TAWAN UNIVERSITY
  • Publication number: 20100264967
    Abstract: A clock and data recovery (CDR) circuit is provided. The CDR circuit receives a data signal and generates a clock signal. The CDR circuit comprises an oscillator, a phase detector, and a first voltage-to-current (V-to-I) converter. The oscillator generates the clock signal according to an oscillation voltage. The phase detector receives the data signal. The phase detector comprises a mixer for detecting a phase difference between the data clock and the clock signal and generating a phase detection signal which represents the phase difference. The first V-to-I converter receives the phase detection signal and generates a first current signal according to a voltage level of the phase detection signal to vary the oscillation voltage.
    Type: Application
    Filed: October 1, 2009
    Publication date: October 21, 2010
    Applicant: NATIONAL TAWAN UNIVERSITY
    Inventors: Jr-I Lee, Ke-Chung Wu