Abstract: A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.

Abstract: A scalable Multiple-Input Multiple-Output (MIMO) detector, comprises an ordering block, a group interference suppression block, a core detector and a residual detector. The ordering block determines an order of the columns of a channel matrix including received streams based on the power thereof. The group interference suppression block coupled to the ordering block groups received streams into a core part and a residual part, the core part including a first received stream and a second received stream corresponding to the first two columns of the channel matrix in the order, the first received stream and the second received stream forming a received signal vector, and the residual part including the rest of the received streams. The core detector detects the core part based on a 2×2 Simplified Maximum Likelihood (SML) detection. The residual detector detects the residual part by Vertical Bell Laboratories Layered Space Time (VBLAST) detection.