Patents Assigned to NATIONAL YANG MING CHIAO TUNG UNIVERSITY
  • Publication number: 20250142780
    Abstract: A heat sink includes a thermally conductive base. The thermally conductive base has a first surface, a second surface, a guiding surface and an accommodating recess. The second surface faces away from the first surface. The guiding surface are connected to the first surface and the second surface. The guiding surface is not perpendicular to the first surface and the second surface. The accommodating recess is located at the first surface. The thermally conductive base has an inner bottom surface and an inner annular side surface which surround and form the accommodating recess. The inner annular side surface is connected to the inner bottom surface. The accommodating recess accommodates a heat source. The inner bottom surface is thermally coupled to the heat source.
    Type: Application
    Filed: August 1, 2024
    Publication date: May 1, 2025
    Applicants: COOLER MASTER CO., LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hao-Jun CHEN, Chi-Chuan WANG
  • Patent number: 12290010
    Abstract: A method for manufacturing a conductive bridging memory device includes the following steps. First, a bottom electrode is formed on a substrate. Next, a switching layer is formed on the bottom electrode. The switching layer is made of a semiconducting metal oxide and free of gallium. Then, a surface of the switching layer is subjected to an oxygen plasma surface treatment. Afterwards, a blocking layer including a conductive material is formed on the treated surface of the switching layer, and an upper electrode is formed on the blocking layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 29, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Chih-Chieh Hsu, Kai-Jhih Gan
  • Publication number: 20250123237
    Abstract: A transistor includes a field effect transistor, a surface modification layer, and a cell detection layer. The field effect transistor includes a source region, a drain region, a channel region, a gate dielectric layer, and a gate. The drain region is spaced apart from the source region in a first direction. The channel extends in the first direction and is disposed between the source region and the drain region. The gate dielectric layer is disposed below the channel region. The gate is disposed below the gate dielectric layer. The surface modification layer is disposed on the channel region. The cell detection layer is disposed on the surface modification layer and includes a plurality of antibodies, wherein the antibodies are configured to identify cell surface antigens, and the cell detection layer is configured to capture cells identified by the antibodies.
    Type: Application
    Filed: March 15, 2024
    Publication date: April 17, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Tai-Ming Ko, Yuh-Shyong Yang, Kuan-Hsing Chen, Che-Ming Lin
  • Publication number: 20250112152
    Abstract: A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Kuan-Ying CHIU, Chee-Wee LIU
  • Patent number: 12260891
    Abstract: A metallic ferroelectric metal (MFM) field effect transistor (FET) is provided that includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: March 25, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Tuo-Hung Hou, Ming-Hung Wu
  • Patent number: 12256559
    Abstract: A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: March 18, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Bing-Yue Tsui, Jui-Cheng Wang
  • Patent number: 12248103
    Abstract: A system and method for LiDAR defogging is disclosed. The method comprises: applying a detection device to determine the fog status and generate a histogram; determining the fog concentration between a target location and the detection device in the histogram according to the histogram; and applying a defogging method to defog the fog concentration between the target location and the detecting device.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 11, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Tzu-Hsien Sang, Sung-You Tsai, Tsung-Po Yu
  • Patent number: 12248055
    Abstract: A method for recognizing a motion state of an object by using a millimeter wave radar having at least one antenna is disclosed. The method includes the following steps. A region is set to select an object in the region, wherein the object has M ranges and M azimuths between the object and the at least one antenna during a first motion time. Each of the M ranges and the M azimuths are projected on a two-dimensional (2D) plane to form M frames. The M frames are sequentially arranged into a first consecutive candidate frames having a time sequence. The first consecutive candidate frames are inputted into an artificial intelligence model to determine a motion state type of the first consecutive candidate frames.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: March 11, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Jiun-In Guo, Hung-Yu Liu
  • Patent number: 12246317
    Abstract: A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 11, 2025
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventor: Chen-Yi Lee
  • Publication number: 20250081604
    Abstract: A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Yi-Chun LIU, Chun-Yi CHENG, Chien-Te Tu, Chee-Wee LIU
  • Publication number: 20250074977
    Abstract: Provided is a method for improving would healing, including administering an effective amount of a chemokine C-C motif ligand 7 (CCL7) antagonist to a subject in need thereof to inhibit CCL7 activity.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Applicant: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Ting-Ting CHANG, Jaw-Wen CHEN
  • Publication number: 20250066788
    Abstract: Provided are compositions and methods of use of a pharmaceutical composition in the manufacture of a medicament for preventing or treating a diabetic kidney disease, the pharmaceutical composition including a chemokine C-C motif ligand 7 (CCL7) antagonist and/or a pharmaceutically acceptable salt thereof and a pharmaceutically acceptable carrier. The medicament can prevent or treat diabetic kidney disease by protecting tubular epithelial cells, reducing glomerular hypertrophy, glomerulosclerosis, and fibrosis. The present disclosure also provides a method for preventing or treating a diabetic kidney disease in a subject in need thereof, including administering an effective amount of a CCL7 antagonist and/or a pharmaceutically acceptable salt thereof to the subject to inhibit an activity of CCL7.
    Type: Application
    Filed: April 29, 2024
    Publication date: February 27, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Ting-Ting Chang, Jaw-Wen Chen
  • Publication number: 20250072030
    Abstract: A device includes a substrate, a semiconductor layer and a ferroelectric layer. The semiconductor layer is over the substrate. The semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. The ferroelectric layer is over the semiconductor layer. The ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Yu-Rui CHEN, Zefu ZHAO, Yun-Wen CHEN, Chee-Wee LIU
  • Publication number: 20250060403
    Abstract: A power device threshold voltage measurement circuit and its operation method thereof are provided. The measurement circuit includes a switch component, a device under test, a common source capacitor and a decoupling capacitor. The switch component and the device under test forms a half bridge circuit and the common source capacitor is in series connected at the source of the device under test. The device under test is connected as a lower switch of the half bridge circuit and the decoupling capacitor is connected between the device under test and the common source capacitor. By applying an OFF-state stress mode and a measurement mode successively afterwards, a threshold voltage of the device under test is obtained. And the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Rustam Kumar, Tian-Li WU
  • Publication number: 20250056782
    Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Tao CHOU, Hsin-Cheng LIN, Ching-Wang YAO, Li-Kai WANG, Chee-Wee LIU, Chenming HU
  • Patent number: 12223698
    Abstract: A method for searching a path by using a 3D reconstructed map includes: receiving 3D point-cloud map information and 3D material map information; clustering the 3D point-cloud map information with a clustering algorithm to obtain clustering information, and identifying material attributes of objects in the 3D point-cloud map information with a material neural network model to obtain material attribute information; fusing the those map information based on their coordinate information, thereby outputting fused map information; identifying obstacle areas and non-obstacle areas in the fused map information based on an obstacle neural network model, the clustering information, and the material attribute information; and generating 3D path information according to the non-obstacle areas. Since the 3D path information is generated based on those map information, the obstacle areas and flight spaces are effectively determined to generate an accurate flight path.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 11, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Mang Ou-Yang, Yung-Jhe Yan, Ming-Da Jiang, Ta-Fu Hsu, Shao-Chun Yeh, Kun-Hsiang Chen, Tzung-Cheng Chen
  • Publication number: 20250044859
    Abstract: A system for navigating a virtual environment using seated walking-in-place footstep locomotion includes a virtual reality device, a first sensing device, and a second sensing device. The first sensing device senses the first footstep locomotion of one of feet of a user seated in a physical environment to generate and transmit a first stepping signal to the virtual reality device. The second sensing device senses the second footstep locomotion of another of the feet of the user seated in the physical environment to generate and transmit a second stepping signal to the virtual reality device. The virtual reality device navigates the virtual environment in a virtual locomotion mode based on a combination of the first stepping signal and the second stepping signal.
    Type: Application
    Filed: May 2, 2024
    Publication date: February 6, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Li-Wei CHAN, Tzu-Wei MI, Chung-Hao HSUEH, Yi-Ci HUANG
  • Publication number: 20250044294
    Abstract: The present invention is related to a use of prochlorperazine (PCP), or analog thereof for treating a cancer in a subject by influencing membrane proteins and receptors and inducing alterations in the expressions of the surface marker on cancer cells and their derived extracellular vesicles. The invention method offers a novel approach for the treatment and diagnosis of cancer and metastasis. Specific surface markers serve as a potential candidate for cancer-associated extracellular vesicles (EVs) and have applications in diagnosis, prognosis, and therapeutic targeting.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Chi-Ying HUANG, Wei-Ni TSAI, Cayla SOLOMON, Tai-Shan CHENG, Ming-Hsi CHUANG, Ly James LEE, Peter Mu-Hsin CHANG, Yu-Tang HUANG, Thi Tuong Linh NGUYEN, Yi-Ning LO
  • Patent number: 12216001
    Abstract: A device and a method for detecting a light irradiating angle are disclosed. The device, used to detect the incident direction of a light ray, includes a solar sensor and a processor. The sensing unit of the solar sensor has sensing areas. The sensing areas correspondingly generate sensing signals based on the intensity of the light ray. A mask covers the sensing unit and has an X-shaped light transmitting portion. The light ray transmits the X-shaped light transmitting portion to form an X-axis light ray and a Y-axis light ray. The X-axis light ray intersects the Y-axis light ray. The X-axis light ray and the Y-axis light ray fall on the sensing area. The processor, coupled to the sensing unit, receives the sensing signals and determines information of the incident direction according to the sensing signals.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 4, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Mang Ou-Yang, Yung-Jhe Yan, Guan-Yu Huang, Tse Yu Cheng, Chang-Hsun Liu, Yu-Siou Liu, Ying-Wen Jan, Chen-Yu Chan, Tung-Yun Hsieh
  • Patent number: 12216446
    Abstract: A ballbar testing tune-up method for machine tool includes the steps of letting a machine tool system execute a ballbar test; obtaining a phase characteristic and a peak-value characteristic; creating a Lagrange interpolation polynomial and inputting a servo controller parameter, a phase characteristic and a peak-value characteristic of the machine tool system each time when executing the ballbar test, and obtaining a proposed servo parameter. This method is simple and easy without incurring additional equipment costs, but just using existing equipment to find the proposed servo parameter quickly and input it into a machine tool system, so as to improve the response issue of a servo system and reduce manufacturing contour error to enhance the working precision of the machine tool system.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 4, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Ching-Hung Lee, Shun-Fu Wu