Abstract: A system for connecting telephony equipment to computer network equipment includes a telephony interface module adapted to accept at least one telephony connection from a telephony network. A computer network interface module is adapted to accept at least one data connection from a computer network. A signal processing module is adapted to alter data to be transferred between the computer network interface module and the telephony interface module. A bypass mechanism is adapted to transfer data between the telephony interface module, the computer network interface module, and the signal processing module while bypassing a host processor connected to the telephony interface module, the computer network interface module, and the signal processing module.

Abstract: A communication switching station includes a digital switch and a sub-rate interface circuit. The switch has signal terminals including inputs and outputs, and switching circuitry, adapted to operate at a first rate, operatively connected between the inputs and outputs. The sub-rate interface circuit includes a first signal terminal operatively connected to at least one of the signal terminals of the first signal terminal and the second signal terminal, the programmable circuitry being operative at a second rate that is lower than the first rate.

Abstract: A method of facilitating telephony communications over a packet-switched network includes detecting signaling tones in an audio stream and blocking them from the stream in response to the detecting. After the blocking, the audio stream is sent over an undependable channel in the packet-switched network. The detected signaling tones can be sent over a dependable channel instead of the undependable audio channel.

Abstract: A communication bus interface circuit includes a local frame signal generator responsive to a device clock signal and having a local bus frame signal output. A synchronization loss detector is responsive to the local frame signal output and to a bus frame signal input. A clock adjuster is responsive to the synchronization loss detector and to the device clock signal to adjust the local frame signal generator until synchronization between the bus frame signal and the local frame signal is established.

Abstract: Apparatus and method for processing serial data signals. In one general aspect, the method features receiving a first serial data signal having a clock frequency and phase, detecting a phase characteristic of the first serial data signal, and delaying the first serial data signal based on the phase characteristic of the first serial data signal to align at least one point in the first serial data signal with at least one point in a system clock signal.

Abstract: A communication circuit includes a dual-channel coder having an unencoded data communication port, a first encoded data communication port, and a second encoded data communication port. The dual-channel coder is operative to translate between unencoded data at the unencoded communication port and corresponding encoded data at both the first encoded data port and at the second encoded data port The circuit further includes a real-time channel interface for connection to a real-time communication channel and operatively connected to the first encoded data tort of the coder. The real-time communication channel has a first latency of a guaranteed maximum for a data element to travel between ends of the real-time communication channel. The circuit further includes a best-efforts channel interface for connection to a best-efforts communication channel and operatively connected to the second encoded data port of the coder.

Abstract: Methods and apparatus for providing an optical bus between circuit boards or other devices is provided.

Abstract: Aspects of the present invention are directed to communications circuits and method that utilize associative memories for providing telephony switching of data between different time slots in one or more time division multiplexed (TDM) serial data lines or streams. The communications circuit may include a first content-addressable memory block and a second content-addressable memory block each of which receive the same address for independently generating tags for accessing a data memory to provide data to or receive data from TDM data lines.