Abstract: A GaN driver circuit is disclosed. The circuit includes a low side switch causing the voltage at an output node to be a first voltage, a high side switch causing the voltage at the output node to be a second voltage in response to a control signal, and a high side switch driver circuit configured to cause the high side switch to apply the second voltage to the output node. The high side switch driver includes a pull-down switch configured to turn off the high side switch in response to an input signal, and a pass gate configured to cause the high side switch to apply the second voltage to the output node by causing the voltage of the control signal to become substantially equal to the second voltage plus a third voltage.

Abstract: A current detecting GaN FET is disclosed. The current detecting GaN FET includes a first GaN switch having a first gate, a first drain, a first source, and a first field plate. The current detecting GaN FET also includes a second GaN switch having a second gate, a second drain, a second source, and a second field plate. The current detecting GaN FET also includes a resistor. The first and second gates are electrically connected, the first and second drains are electrically connected, and the resistor is connected between the first and second sources.

Abstract: A GaN half bridge circuit is disclosed. The circuit includes a bootstrap power supply voltage generator is configured to supply a first power voltage and includes a switch node. The circuit also includes a bootstrap transistor, a bootstrap transistor drive circuit, and a bootstrap capacitor connected to the switch node and to the bootstrap transistor. The bootstrap capacitor is configured to supply the first power voltage while the voltage at the switch node is equal to the second switch node voltage, the bootstrap transistor is configured to electrically connect the bootstrap capacitor to a power node at a second power voltage while the voltage at the switch node is equal to the first switch node voltage, and the bootstrap power supply voltage generator does not include a separate diode in parallel with the drain and source of the bootstrap transistor.

Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.

Abstract: A GaN resonant circuit is disclosed. The GaN resonant circuit includes a power switch configured to be selectively conductive according to one or more gate signals, and configured to generate a switch signal indicative of the value of the current flowing therethrough. The GaN resonant circuit also includes a power switch driver, configured to generate the gate signals in response to one or more control signals, where the power switch driver is configured to cause the power switch to become nonconductive in response to the switch signal indicating that the value of the current flowing through the power switch has transitioned across a threshold value.

Abstract: A DC-AC converter is disclosed. The DC-AC converter generates an output AC signal, and has an input DC-AC converter which generates a first AC signal, a transformer device which receives the first AC signal and generates a second AC signal, and a first bidirectional switch which selectively connects a first transformer output terminal and a first output terminal. The DC-AC converter also has a first capacitor which powers the first bidirectional switch, a first charging circuit which charges the first capacitor, and a second bidirectional which selectively conduct connects a second transformer output terminal and a second output terminal. The DC-AC converter also has a second capacitor which powers the second bidirectional switch, and a second charging circuit which charges the second capacitor. Each of the bidirectional switches includes series connected transistors between first and second input/output terminals, and a transistor driver which drives the transistors.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: A GaN half bridge circuit is disclosed. The circuit includes a bootstrap power supply voltage generator is configured to supply a first power voltage and includes a switch node. The circuit also includes a bootstrap transistor, a bootstrap transistor drive circuit, and a bootstrap capacitor connected to the switch node and to the bootstrap transistor. The bootstrap capacitor is configured to supply the first power voltage while the voltage at the switch node is equal to the second switch node voltage, the bootstrap transistor is configured to electrically connect the bootstrap capacitor to a power node at a second power voltage while the voltage at the switch node is equal to the first switch node voltage, and the bootstrap power supply voltage generator does not include a separate diode in parallel with the drain and source of the bootstrap transistor.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.

Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

Abstract: A GaN driver circuit is disclosed. The circuit includes a low side switch causing the voltage at an output node to be a first voltage, a high side switch causing the voltage at the output node to be a second voltage in response to a control signal, and a high side switch driver circuit configured to cause the high side switch to apply the second voltage to the output node. The high side switch driver includes a pull-down switch configured to turn off the high side switch in response to an input signal, and a pass gate configured to cause the high side switch to apply the second voltage to the output node by causing the voltage of the control signal to become substantially equal to the second voltage plus a third voltage.

Abstract: A half bridge circuit is disclosed. The circuit includes a GaN-based substrate, an oscillator on the substrate, and one or more components forming one or more of a low side power transistor, a low side driver, low side logic circuitry, a high side power transistor, a high side driver, and high side logic circuitry. At least one of the low side power transistor, the low side driver, the low side logic circuitry, the high side power transistor, the high side driver, and the high side logic circuitry is at least partially formed on the substrate. The oscillator is configured to generate non-overlapping pulses, and the non-overlapping pulses are separated by a dead time.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: A converter circuit is disclosed. The converter circuit includes a transformer and a primary circuit connected to the primary side of the transformer, where the primary circuit includes a first switch connected to a ground. The converter circuit also includes a second switch connected to the first switch, and a clamping capacitor connected to the second switch and to the input. The converter circuit also includes a secondary circuit connected to the secondary side of the transformer, where the secondary circuit includes a secondary capacitor, an inductor, and a bypass element in parallel with the inductor.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Abstract: A lateral transistor includes a source a gate and a drain connection to a transition layer within a semiconductor substrate. One or more capacitively coupled floating field plates are connected to the source connection such that the source voltage is uniformly distributed across the field plates.

Abstract: A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

Abstract: A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.