Patents Assigned to Nazomi Communications, Inc.
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Patent number: 8769508Abstract: A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.Type: GrantFiled: June 29, 2005Date of Patent: July 1, 2014Assignee: Nazomi Communications Inc.Inventor: Mukesh K. Patel
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Patent number: 8473718Abstract: A hardware Java accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.Type: GrantFiled: October 3, 2006Date of Patent: June 25, 2013Assignee: Nazomi Communications Inc.Inventor: Mukesh K. Patel
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Patent number: 8185882Abstract: A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.Type: GrantFiled: February 14, 2006Date of Patent: May 22, 2012Assignee: Nazomi Communications Inc.Inventors: Mukesh K Patel, Jay Kamdar, Veeraganti R. Ranganath
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Patent number: 7290080Abstract: In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.Type: GrantFiled: April 1, 2003Date of Patent: October 30, 2007Assignee: Nazomi Communications Inc.Inventor: Mukesh K. Patel
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Patent number: 7225436Abstract: A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.Type: GrantFiled: October 13, 2000Date of Patent: May 29, 2007Assignee: Nazomi Communications Inc.Inventor: Mukesh K. Patel
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Patent number: 7080362Abstract: A hardware Java™ accelerator is provided to implement portions of the Java™ virtual machine in hardware in order to accelerate the operation of the system on Java™ bytecodes. The Java™ hardware accelerator preferably includes Java™ bytecode translation into native CPU instructions. The combination of the Java™ hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java™ programs for use in commercial appliances.Type: GrantFiled: August 24, 2001Date of Patent: July 18, 2006Assignee: Nazomi Communication, Inc.Inventors: Mukesh K. Patel, Jay Kamdar, V. R. Ranganath
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Patent number: 6826749Abstract: A Java accelerator includes a hardware unit associated with the CPU portion, the hardware unit converting stack-based instructions, such as Java bytecodes, into register-based instructions such as the instructions which are native to the CPU. A thread lifetime unit in the hardware unit is used to maintain a count of the number of bytecodes to be executed while an active thread is loaded into the system. Once this count reaches zero or below, the operation of a/the thread in the system is stopped and the Java Virtual Machine loaded into the CPU portion in order to implement its thread manager. Additionally, a single step unit in the hardware unit allows the production of debugger indications after each stack-based instruction.Type: GrantFiled: May 25, 2001Date of Patent: November 30, 2004Assignee: Nazomi Communications, Inc.Inventors: Mukesh K. Patel, Udaykumar R. Raval, Harihar J. Vyas
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Patent number: 6338160Abstract: An implementation of Java is disclosed in which references to the constant pool are implemented by using a Data Resolution Field within the constant pool entry. The Data Resolution Field acts as an index to a jump table to jump to resolve the reference or to perform the bytecode instruction. When the reference is resolved, the contents of the Data Resolution Field in the constant pool entry are modified so that the next time the bytecode is run, the resolution steps need not be done.Type: GrantFiled: January 20, 2000Date of Patent: January 8, 2002Assignee: Nazomi Communications, Inc.Inventors: Mukesh K. Patel, Chitrabhanu Dasgupta
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Patent number: 6332215Abstract: A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.Type: GrantFiled: December 8, 1998Date of Patent: December 18, 2001Assignee: Nazomi Communications, Inc.Inventors: Mukesh K. Patel, Jay Kamdar, V. R. Ranganath