Abstract: A boost converter includes an inductor and a diode electrically connected in series between an input voltage and an output voltage; a transistor electrically coupled to an interconnected node of the inductor and the diode; and a controller that controls switching of the transistor according to a transient mode and an estimated load current. The output voltage in a light-to-heavy load transient mode has at least one first valley point with a value of a transient voltage threshold, followed by at least one second valley point with a value higher than the first valley point, before exiting the light-to-heavy load transient mode.

Abstract: An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

Abstract: A Doppler radar sensor includes a radar and a bondwire interconnection. The bondwire interconnection is connected to a signal generator and an antenna of the radar and configured to transmit a radio frequency signal generated by the signal generator to the antenna and transmit a reflected signal received by the antenna to a demodulator of the radar. A metal strip, a first shunt bondwire and a second shunt bondwire of the bondwire interconnection can be used as a matching circuit of the antenna to decrease the transmission loss and increase the detection distance of the radar.

Abstract: A reliability based keyframe switching system adaptable to iterative closest point (ICP) includes a camera that captures frames; a matching device that determines corresponding pairing between the frames for an ICP operation to form a set of plural point-pairs; a transformation device that performs transformation estimation to estimate transformation that minimizes distances of the point-pairs, and determines whether the estimated transformation converges; and a reliability device that determines whether the ICP operation is reliable, and replaces a current keyframe with a new keyframe if the ICP operation is determined to be unreliable.

Abstract: A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.

Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.

Abstract: A digital constant on-time controller adaptable to a direct-current (DC)-to-DC converter includes a current sensing circuit that senses stored energy of the DC-to-DC converter, thereby generating a sense voltage; a semi-amplitude detector that detects half of a peak-to-peak amplitude of the sense voltage, thereby generating a semi-amplitude voltage; a DC voltage detector that detects a DC voltage across an effective series resistor of an energy storage circuit that provides the stored energy of the DC-to-DC converter, thereby generating a DC voltage; an arithmetic device that adds the sense voltage and the semi-amplitude voltage, from which the DC voltage and a predetermined reference signal are subtracted; and a pulse-width modulation (PWM) generator that generates a switch control signal according to a result of the arithmetic device.

Abstract: A motion-aware keypoint selection system adaptable to iterative closest point (ICP) includes a pruning unit that receives an image and selects at least one region of interest (ROI) composed of a selected subset of points on the image; a point quality estimation unit that generates point quality of each point in the ROI according to a frame rate; and a suppression unit that receives the point quality and generates keypoints by screening the ROI.

Abstract: A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k?1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.

Abstract: A motion-aware keypoint selection system adaptable to iterative closest point (ICP) includes a pruning unit that receives an image and selects at least one region of interest (ROI) composed of a selected subset of points on the image; a point quality estimation unit that receives the ROI and generates point quality; and a suppression unit that receives the point quality and generates keypoints. In one embodiment, a near edge region (NER) is selected as the ROI. In another embodiment, the point quality estimation unit generates point quality according to point motion and point depth.

Abstract: A simulated-evolution-based macro refinement method includes evaluating a score of each placed macro cell to be refined; generating a random number; determining whether the score satisfies a predetermined condition; placing the macro cell into a queue if the score associated with the macro cell satisfies the predetermined condition; and sorting and placing macro cells of the queue according to scores of the macro cells in the queue.

Abstract: A geometric camera calibration system includes an extrinsic iterative closest point (ICP) device that generates an estimated extrinsic matrix by adjusting an initial extrinsic matrix according to first 3D points in camera coordinates; and an intrinsic ICP device that receives 3D points in chessboard coordinates and accordingly generates an error metric between the 3D points in chessboard coordinates and predetermined second reference 3D points. The extrinsic ICP device performs ICP operation to minimize difference between the 3D points in camera coordinates and predetermined first reference 3D points. A current intrinsic matrix is then outputted as an updated intrinsic matrix if a current error metric is not greater than a previous error metric.

Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m?1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.

Abstract: A method of macro placement includes partitioning an entire region of a semiconductor chip into sub-regions; determining a packing sequence of a plurality of movable macros in the sub-region; extracting search points of a plurality of placed blocks in the sub-region with respect to one of the movable macros; determining a feasible region associated with the search point; packing said movable macro in the feasible region; evaluating a legalizing cost function; and determining whether a value of the evaluated legalizing cost function is less than a predetermined threshold value.

Abstract: A high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.

Abstract: A system of selecting a keyframe for iterative closest point (ICP) includes a reference frame selector that generates a reference frame according to a current frame and a current keyframe; an ICP loop unit that performs ICP on the reference frame and the current frame, thereby generating a pose of the current frame; and a keyframe update unit that generates a new keyframe according to an offset condition between the pose of the current frame and a pose of the reference frame.

Abstract: A low order filter circuit having a frequency correction function, a frequency correction method for a low order filter circuit, and a high order filter circuit are provided. An analog to digital converter (ADC) may detect a peak of a signal processed by a second order filter unit, and after comparison and determination are performed by a digital correction unit, a frequency control signal is outputted as a feedback to a notch filter or a band-pass filter in the second order filter unit where frequency adjustment is performed. The high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.

Abstract: An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.