Patents Assigned to nCorium
  • Interleaving in multi-level data cache on memory bus
    Patent number: 11698873
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 11, 2023
    Assignee: nCorium
    Inventor: Arvindhkumar Lalam
  • Multi-level data cache and storage on a memory bus
    Patent number: 10747694
    Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 18, 2020
    Assignee: nCorium
    Inventor: Arvindhkumar Lalam