Abstract: Write-leveling, a write-leveling control unit(250) adjusts the delay amounts of DQS control unit(242) and a DQ control unit(244), at first, within a range of less than one clock cycle. Then, with respect to each SDRAM(282), a read-data row acquired by performing a read after a write of an expected value data row is compared value data row, and depending upon the comparison result, the delay amounts of the DQS control unit(242) and the DQ control unit(244) are adjusted in clock-cycle units. At the above write-time, control is performed so that the DQS control unit(242) outputs a data strobe signal(DQS) which is 2×M clock cycles longer than a burst length defined according to a specification, and the DQ control unit(244) adds M units each of data before and after a number of units of expected value data rows that match the burst length in order to output the data.

Abstract: An object of the present invention is to provide an electronic device in which a temperature control using a cooling fan can be made more efficiently and more stably and a method for controlling temperature of a device. The device includes the fan, a measurement unit, and a control unit which controls a rotation speed of the fan based on the measured temperature. The control unit stores a plurality of measured temperatures and a normal temperature range for each measurement unit, determines the presence or absence of a temperature increasing trend, shortens a time interval when it is determined that increases, determines whether or not the plurality of temperatures are included in the normal range when it is determined that does not increase, prolongs when the all are included in the normal range, and does not change when at least one is not included in the normal range.

Abstract: Disclosed is a cooling device which can perform cooling with suppressed power consumption and noise even when temperature sensor is in failure without increasing cost. The cooling device includes a temperature estimation unit which, if a failure is detected in at least one of heat source temperature sensors (HSTSs) measuring temperature of the heat sources (HSs), estimates a value to have been measured by the failed HSTS based on measured values by the HSTSs not in failure, a measured value by an exhaust temperature sensor measuring an exhaust temperature which is temperature of an air outlet for discharging heat generated by HSs from a housing containing the HSs, and information representing a temperature distribution characteristic within the housing; and a rotational frequency calculation unit which calculates a rotational frequency of a cooling fan which rotates based on the estimated value and the measured values by the HSTSs not in failure.

Abstract: A memory access control device has a memory control unit and a software execution unit executing software. The memory control unit has: a data transmission unit configured to perform multicast transfer that reads a data from the memory and transmits the data to data transfer destinations through a network; a data reception unit configured to receive multicast transfer data from the network; and a reception data counter configured to indicate a number of multicast transfer data received by the data reception unit. The software execution unit instructs the memory control unit to perform a plurality of multicast transfers and then reads respective reception data counters of the data transfer destinations for each checkpoint in sequence of the software to determine completion of the plurality of multicast transfers.

Abstract: An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory.

Abstract: Provided is a technique of compensating time degradation of a CPU and maintaining performance of an electronic device without disturbing a normal operation of the electronic device. A maintenance apparatus includes: a degradation information acquisition unit that acquires degradation information from a sensor circuit integrated in a CPU when the CPU performs a normal operation, the degradation information varying according to degradation of the CPU; a degradation level determination unit that determines a degradation level based on the degradation information, the degradation level indicating a degree of progression of degradation of the CPU; and a power supply control unit that controls a power supply to increase a power supply voltage applied to the CPU with increasing the degradation level.

Abstract: The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of target instructions created beforehand collectively, thereby processing those instructions collectively according to the coding when those target instructions are combined so as to be processed collectively and a memory for storing the collective emulation coding.

Abstract: A first reception unit receives “ambient temperature” which is a temperature of surroundings where the computer is installed. A second reception unit receives “first device temperature” which is a temperature of a first device provided in the computer. A third reception unit receives “second device temperature” which is a temperature of a second device provided in the computer. A fan rotation speed indicating unit determines the rotation speed of the fan based on a comparison between the ambient temperature, first device temperature, and second device temperature which are received by the first to third reception units and a fan rotation speed description table describing a relationship between the respective temperature and fan rotation speed and instructs the fan to rotate at the determined rotation speed.

Abstract: A memory system includes a memory module of first to eighth semiconductor memories of an n-bit input/output type; and a memory control unit configured to generate three n-bit error detection and correction codes based on four n-bit data received from an external system, respectively store the four n-bit data in the first to fourth semiconductor memories, and respectively store the three n-bit error detection and correction code in the fifth to seventh semiconductor memories. When reading the four n-bit data stored in the first to fourth semiconductor memories, the memory control unit executes error detection to every two of the four n-bit data read from the first to fourth semiconductor memories based on the three n-bit error detection and correction code stored in the fifth to seventh semiconductor memories and executes error correction to one n-bit data related to an error, of the four n-bit data.

Abstract: To provide a mirroring device which does not need a competition control function dedicated for a restoring process without halting other access commands during the restoring process of a mirroring. The mirroring device includes a pair of storage devices, a mirroring control unit which duplicates write data in the storage device in the case that a pair of storage devices are in a normal state and writes data in an available storage device in the case of a reduced state, a cache unit which stores input and output data and rewrites target data to be rewritten in the pair of storage devices, and a mirroring recovery unit which readouts date to the cache unit from the available storage device in the reduced state and recovers duplication of data by rewriting to the pair of storage devices when recovering from the reduced state to the normal state.

Abstract: One aspect of the present invention is a memory controller which controls a memory device including two or more memory access units and includes a data control circuit and an adjusting circuit that performs at least one of a first processing and a second processing. In the first processing, a timing of the write strobe signal generated by the data control circuit in a write operation is adjusted for each memory access unit and a write strobe adjusting signal specifying a timing for each memory access unit to load write data is generated, and in the second processing, a timing of the read strobe signal generated by the memory device in a read operation is adjusted for each memory access unit and a read strobe adjusting signal specifying a timing for the data control unit to read data read out from each memory access unit is generated.

Abstract: The present invention determines an incorrect packet from a faulty partition quickly and reliably and prevents the packet from flowing into normal partitions through simple control actions. The multi-partition computer system is a multi-partitioned computer system in which a plurality of nodes are logically divided into a plurality of partition, and each node contained in the partitions includes a packet identification unit which, upon receiving a packet, compares the partition identification information uniquely assigned to own partition against the partition identification information contained in the receive packet, and if these pieces of information do not match each other, judges and discards the receive packet as an incorrect packet.

Abstract: A multiprocessor system includes a plurality of nodes, each of which includes a plurality of processors, a plurality of memories, and first and second node controllers. Unique identifiers are assigned to all the components.

Abstract: A computer system includes a plurality of buses; a device connected with the plurality of buses and configured to generate an error message when a failure has occurred on a first bus of the plurality of buses; and an IO control circuit connected with the device and configured to close the first bus in response to the error message transaction. The device includes a plurality of bus control sections respectively connected with said plurality of buses. The IO control circuit transfer a first operation transaction to the first bus through a first bus control section, and closes the first bus in response to the error message transaction in a bus failure operation when the failure has occurred on the first bus.

Abstract: The invention is to provide a mode setting method and a system including a PCI bus in the hot plug of a PCI device which is capable of supporting a platform unique function for a PCI device that is hot-added. Therefore, in a system including a PCI bus according to an exemplary embodiment of the invention, a south bridge directly notifies firmware that a PCI device is hot-added and thus, it is possible to support the platform unique function for the hot-added PCI device without modifying an OS or an open hot plug driver.

Abstract: When receiving a write message associated with data, an input/output controller issues a write-request message to a home processor node which holds the data in a memory. When receiving the write-request message, a memory controller in the processor node executes a consistency process on the basis of information, regarding the state of the data, stored in a directory, and sends a write-permission message to the input/output controller which has issued the write-request message. In response to the received write-permission message, the input/output controller in an input/output node issues an update message, serving as a write message, to the home processor node. In response to the received update message, the memory controller in the process node updates the data in the main memory. In the above process, when receiving a plurality of write messages from input/output devices, the input/output controller issues write-request messages irrespective of the progress of a preceding write message.

Abstract: An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory.

Abstract: An apparatus includes a memory including a controller for initializing the memory, the controller storing a first data including a first code for correcting a first error of the first data, to the memory when initializing, and a memory controller controlling a data transmission to the memory, the memory controller being connected to the memory. The memory controller includes a code generation circuit storing a second data including a second code, to the memory after the initializing, the second code including an address parity for detecting an address causing a second error of the second data in said memory.

Abstract: A computer system includes a plurality of buses; a device connected with the plurality of buses and configured to generate an error message when a failure has occurred on a first bus of the plurality of buses; and an IO control circuit connected with the device and configured to close the first bus in response to the error message transaction. The device includes a plurality of bus control sections respectively connected with said plurality of buses. The IO control circuit transfer a first operation transaction to the first bus through a first bus control section, and closes the first bus in response to the error message transaction in a bus failure operation when the failure has occurred on the first bus.

Abstract: The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of target instructions created beforehand collectively, thereby processing those instructions collectively according to the coding when those target instructions are combined so as to be processed collectively and a memory for storing the collective emulation coding.