Abstract: Disclosed is an apparatus including an odd data receiving unit that receives an input signal, an even data receiving unit that also receives the input signal, and a pattern filter. The odd data receiving unit samples a half-rate DFE equalized signal with an odd data timing clock to output data decision data. The odd data receiving unit also samples both the half-rate DFE equalized signal and a non-half-rate DFE equalized signal with an odd edge timing clock having the phase shifted by 90 degrees from the odd data timing clock to output resulting edge decision data. The even data receiving unit samples the half-rate DFE equalized signal with an even data timing clock having the phase shifted by 180 degrees from the odd data timing clock to output data decision data.