Patents Assigned to NEC Corparation
  • Publication number: 20230098126
    Abstract: The present invention provides a shop system (10) including: an acquisition unit (13) that acquires, from an information acquisition terminal (12), person-related information about a person who visits a shop; a determination unit (14) that determines, based on the person-related information, whether to permit the person who visits the shop to enter the shop; and an operation control unit (16) that controls, based on a result of the determination, operation of a shop entry control apparatus (11) that controls entry into the shop.
    Type: Application
    Filed: December 24, 2020
    Publication date: March 30, 2023
    Applicant: NEC Corparation
    Inventors: Takahiro MATSUI, Jun UCHIMURA, Yasuyo KAZO
  • Publication number: 20220417623
    Abstract: A data management apparatus (20) includes a data acquisition unit (210), a municipality information generation unit (220), and a storage processing unit (230). The data acquisition unit (210) acquires data generated by a sensor apparatus installed along a road in association with sensor identification information capable of identifying the sensor apparatus. The municipality information generation unit (220) generates, by using the sensor identification information, municipality information indicating a municipality that manages a location where the sensor apparatus is installed. The storage processing unit (230) stores the data acquired by the data acquisition unit (210) in a data storage unit (232) in association with the municipality information generated by the municipality information generation unit (220).
    Type: Application
    Filed: December 27, 2019
    Publication date: December 29, 2022
    Applicant: NEC Corparation
    Inventors: Manaka YAJIMA, Daisuka Nakayama, Yukiko Nakayama
  • Patent number: 6333915
    Abstract: An on-line line monitor system is provided for fault diagnosis of signal processing blocks, which perform cross-connecting of ATM cells by using at least reception-side memory blocks, a SRAM block and transmission-side memory blocks under control of a CPU block with respect to an operating line system, which is presently placed in an on-line state to be in communication service, and a spare line system which is placed in a standby state to be out of the communication service. Test ATM cells are sequentially input to the signal processing blocks, in which they are processed and are then output together with normal ATM cells. By comparing the processed test ATM cell with the original test ATM cell, it is possible to determine occurrence of fault in the signal processing blocks. When the fault is detected with respect to the operating line system, line control is switched over to the spare line system. In addition, the on-line line monitor system monitors a pileup state of the normal ATM cells in the SRAM block.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: December 25, 2001
    Assignee: NEC Corparation
    Inventor: Yoshitaka Fujita