Abstract: For selectively removing a silicon nitride film formed on a bottom of a contact hole or the like in a semiconductor device, plasma etching is performed using a process gas supplied therefor which is comprised of a first fluorine compound including a carbon atom-carbon atom bond [for example, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), octafluorocyclopentene (C5F8)], and a second fluorine compound including at least one hydrogen atom and a single carbon atom in one molecule (for example, fluoromethane (CH3F) , difluoromethane (CH2F2), trifluoromethane (CHF3)]. According to this method, the silicon nitride film on the bottom can be selectively removed without removing a silicon nitride film formed on a side wall of the contact hole and the like.

Abstract: A method for simply forming a miniature contact hole in a self-aligned manner with a wiring layer. A gate insulating film, a gate electrode, and a protective insulating layer are formed on the surface of a silicon substrate, and a blanket insulating film is deposited over the entire surface to cover a source/drain diffusion layer. Subsequently, an interlayer insulating film is laminated on the blanket insulating film. Nitrogen is added to a mixture gas of C5F8 and O2, and the resulting mixture gas is excited by a plasma for use as an etching gas. The interlayer insulating film is etched by reactive ion etching (RIE) using the blanket insulating film as an etching stopper to form a contact hole. A silicon nitride film is preferably used for the protective insulating layer. A silicon nitride film or a silicon carbide film is preferably used for the blanket insulating film.

Abstract: A semiconductor memory device includes two memory cell array sections, a single clock signal line, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal based on a second clock signal externally supplied and outputs the first clock signal onto the clock signal line. The first clock signal has twice of a frequency of the second clock signal. The multiplexer section is connected with the clock signal line and outputs first data and second data respectively read out from the two memory cell array sections in order during one period of the second clock signal in response to the first clock signal on the clock signal line.