Abstract: An operational amplifier having an input stage including a differential transistor pair and an output stage receiving an output of the input stage for outputting an output signal having a wide output range. The input stage includes a field effect transistor connected in parallel to a constant current source for the differential transistor pair and having a gate connected to receive a level-shifted signal of an output of the input stage, so that when the output signal of the output stage changes, the field effect transistor is turned on so as to supplying an additional bias current to the differential transistor pair in addition to a bias current supplied by the constant current source, so that the slew rate of the output signal of the output stage is elevated.

Abstract: To provide an OSD circuit needing little load for the control command transfer for displaying a background color, a OSD circuit of the invention comprises a background color control circuit (4) for out-putting three color signals and a blanking signal generated by a character generator (3), when a background control signal supplied from the command processor is inactive, said background control signal made active when the video picture is to be replaced with a background color, and outputting the three color signals generated by the character generator during the blanking signal is active and background color signals for displaying the background color during the blanking signal is inactive, together with a background blanking signal for suppressing signals of all of the video picture instead of the blanking signal, when the background control signal is active.

Abstract: A compact level control circuit without using a shield structure is suitably provided in a small space such as a portable radio communication apparatus. A level control circuit for a portable radio communication apparatus arranged by: a first variable attenuator into which an input RF (radio frequency) signal is supplied, the attenuation amount of which is controlled based upon a first level control signal, and which outputs a first attenuated RF signal; a frequency converter for frequency-converting the first attenuated RF signal into a predetermined intermediate frequency band signal to thereby output a first IF (intermediate frequency) signal; a second variable attenuator into which the first IF signal is supplied, the attenuation amount of which is controlled based on the first level control signal, and which outputs a second attenuated IF signal; and a bandpass filter for outputting only said predetermined intermediate frequency band component of the second attenuated IF signal.

Abstract: In a main signal memory supervisory control system which comprises a parity generator, a parity detector, a write address counter and a read address counter, a state management section, a down counter, and a change point detector are arranged as memory supervising means. In this memory supervisory, a state management section receives address generation notifications from the write address counter and the read address counter to calculate and outputs the data accumulation amount of the main signal memory, a down counter subtracts a counter by the read address, sets a predetermined value of a data amount in advance, outputs a change notification when a counter value changes from numerical value "1" to numerical value "0", and loads the predetermined value on the counter, and a change point detector sends an odd-even switching signal of a parity when the change point detector receives the change notification.

Abstract: A first groove for an upper interconnection and a second groove for a bonding pad are formed on a silicon dioxide film including a lower interconnection, and a through-hole is formed to connect the first groove to the lower interconnection. At the same time with the formation of the through-hole, the second groove is deepened by the common etching process. Then, an Al film is formed on the silicon dioxide film, and the Al film is polished to be removed except for the Al film in the first and second grooves to provide the upper interconnection and the bonding pad.

Abstract: Tips of emitters are protruded over a control electrode in a field emission cathode. The cathode is a part of an input cavity, and an anode facing the cathode is also a part of the input cavity. A voltage which is in the vicinity of a threshold value or less than the threshold value is applied across the control electrode and the emitters, so that an emission current is modulated in density by a RF input signal.

Abstract: In a magnetic disk drive, a shock absorbing device has recesses formed in the base of the disk drive, and elastic shock absorbing members respectively fitted in the recesses. In an unstressed position, the highest point or apex of each shock absorbing member is higher than a mount face in which the recess is formed. A suitable gap exists between the outer periphery of the shock absorbing member and the inner periphery of the recess. When the base of the disk drive is affixed to the housing of a system body, the shock absorbing member is deformed and is fully received in the recess because of the gap. When the disk drive is caused to fall down by accident, the shock absorbing device reduces the impact to be imparted to mechanisms mounted on the base.

Abstract: Reproduced signals from detectors 1a to 1c installed in an optical head are level-adjusted by amplifiers 2a to 2c. Output signals of the amplifiers 2a and 2b are delayed by respective delay circuits 6a and 6b. An output signal of the delay circuit 6b and an output signal of the amplifier 2c are subtracted from an output signal of the delay circuit 6a by an adder 4. A reproduced signal from which cross-talk resulting from the adjacent track has been removed is obtained from the adder 4. The delay amounts of the delay circuits 2a and 2b are set according to delay control signals 8a and 8b. The delay amounts are set when accessing to a fixed pattern recording area disposed on a predetermined position of the optical disk. A control circuit 5 measures a time difference between the output signal of the detector 1b and the output signal of the detector 1c to output a delay control signal 8a.

Abstract: An interpreter linkage system sequentially interprets a plurality of statements constituting a source program written in a programming language in order to sequentially execute them. The system is further capable of arbitrarily adding new statements to an original set of statements by providing sequentially linked extension interpreters capable of interpreting a plurality of specific statements uninterpretable by a basic interpreter. Linkage information relates the basic interpreter to the extension interpreters so that each of the specific statements included in the source program is interpreted by any one of the extension interpreters which are sequentially linked.

Abstract: For improvement in switching speed, there is provided a Schmit trigger circuit comprising a high-voltage supply line, a low-voltage supply line, a series combination of a bipolar transistor and a resistor provided between the high-voltage supply line and the low-voltage supply line, the bipolar transistor having a base node connected to an input terminal, an intermediate node provided between the bipolar transistor and the resistor, a logic gate having an output node and two input nodes connected to the input terminal and the intermediate node, respectively, and a field effect transistor operative to establish or block a current path between the intermediate node and one of the high-voltage supply line and the low-voltage supply line, the field effect transistor having a gate node connected to the output node of the logic gate.