Abstract: Provided is a display device drive circuit capable of setting an optimum drive performance for each output amplifier without increasing the chip size. The display device drive circuit includes: at least two bias lines having different reference potentials; a selector that selects one of the bias lines based on a grayscale signal; and an output amplifier that is supplied with a reference potential of the one of the bias lines selected by the selector, generates a display signal, and supplies the display signal to a data line.

Abstract: A band pass filter circuit, wherein the band pass filter passes a frequency band between a first cutoff frequency and a second cutoff frequency with respect to an input frequency of an input signal, the band pass filter circuit includes: a first resonant circuit; a second resonant circuit; a third resonant circuit; at least one of a capacitive circuit and an inductive circuit. The first resonant circuit is connected to a signal line in series and sets a first resonant frequency as the first cutoff frequency. The second resonant circuit is connected to the signal line in series and sets a second resonant frequency as the second cutoff frequency. The third resonant circuit is connected to the signal line in parallel at a node where the first and second resonant circuits are connected, and sets a third resonant frequency as a band-pass center frequency between the first and second cutoff frequencies.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion devices, a charge transfer device for transferring a signal charge converted by the photoelectric conversion devices, a signal charge detection portion for converting a signal charge transferred by the charge transfer device into a signal voltage, a reset circuit for resetting a potential of the signal charge detection portion, and an amplification portion for amplifying the signal voltage. The amplification portion includes a two-stage source follower, each supplied with power supply voltages different from the power supply voltage to be supplied to the reset circuit. The second stage source follower includes drive transistor, and a current source that changes a current amount according to a fluctuation of the reset potential VRD.

Abstract: Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.

Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.