Abstract: An optical communication module includes a CAN member including a conductive stem member where an optical electronic device is mounted and a conducive lens cap that holds an optical lens optically coupled with the optical electronic device, is connected to the stem member in a conductive state, and covers a surrounding portion of the optical electronic device; a conductive cylindrical holder which is disposed around the lens cap, is fixed to the CAN member in an insulation state through an insulating resin, and is provided with an opening facing the optical lens; and an optical receptacle including an optical member that is optically coupled with the optical lens and the optical electronic device through the opening and a holding frame that holds the optical member inside.

Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

Abstract: A method that divides semiconductor integrated circuit devices (corresponding to S1 and S2) into a plurality of groups and tests them simultaneously has the semiconductor integrated circuit devices operate with a clock signal (corresponding to CLK1 and CLK2) having a frequency different from that in other groups in at least one group. A test is performed without decreasing the number of chips tested at one time.

Abstract: A semiconductor device includes a CDR (Clock Data Recovery) circuit and a frequency tracking control circuit. The CDR (Clock Data Recovery) circuit executes a clock data recovery on a serial data inputted synchronously with a spread spectrum clock. The frequency tracking control circuit controls a bandwidth of frequency which can be tracked by the CDR circuit.

Abstract: A differential amplifier includes a differential amplifier section to generate a current composed of a differential-mode current and a first common-mode current according to a differential-mode component and a common-mode component of an input signal, a common-mode current generator section to generate a common-mode current according to the common-mode component of the input signal, and a current amplifier section to receive the current and the common-mode current, amplify a difference between the current and the common-mode current and output a result.

Abstract: A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.

Abstract: A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.

Abstract: A program tamper detecting apparatus includes an external memory, an activation ROM and a CPU. The external memory stores a first code for program tamper detecting and a first program, wherein the first program is encrypted. The activation ROM stores a second program for decrypting the first program. The CPU is electrically connected to the external memory and the activation ROM. The CPU decrypts the first program by executing the second program to obtain the decrypted first program. The CPU detects tampering of the first program based on a comparison between the first code and a result of a predetermined operation executed on second codes of the decrypted first program.

Abstract: Provided is a semiconductor apparatus that reduces on-resistance in wiring between a first electrode terminal and a second electrode terminal. The semiconductor apparatus includes the first electrode terminal, the second electrode terminal, and at least two wires that connect the first and second electrode terminals. At least two wires are electrically connected with each other by using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode, for example. The second electrode terminal is a terminal of a source electrode of a MOSFET, for example.

Abstract: A computer system increases the confidentiality of a memory to be protected and prevents invalid access that is made, for example, by replacing the memory. The computer system includes a memory in which state information AA, which indicates whether or not information to be protected is stored in a predetermined memory area, and access permission information BB, which indicates whether or not access to the memory area is permitted, are stored; and an access control unit that rewrites the state information AA when information to be protected is written to, or deleted from, the memory area and at the same time, when the system is started, rewrites the access permission information BB to permit access to the memory area if information to be protected is not written in the memory area but, otherwise, rewrites the access permission information BB to the access inhibition state.

Abstract: A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.

Abstract: A driver circuit including a pre-driver B1 that operates by receiving operating power from a first power supply VDDI, and a main-driver B2 that receives operating power from a second power supply VDDE, amplifies an output signal from the pre-driver B1, and outputs the amplified signal. It also includes a first switch B4 between the first power supply VDDI and the pre-driver B1. It also includes a second switch B5 between the second power supply VDDE and the main-driver B2. A overvoltage protection sequence circuit B3 controls the On/Off states of the first switch B4 and the second switch B5 to controls the On/Off order of the pre-driver B1 and the main-driver B2. By doing so, the overvoltage protection sequence circuit B3 prevent an overvoltage from being applied to the driver circuit, especially to the main-driver B2.

Abstract: A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.

Abstract: A microcomputer system according to the present invention includes multiple backup power supplies that are used instead of the main power supply in response to a voltage drop of a main power supply. The microcomputer system further includes a backup power supply monitoring circuit that monitors charge amount of the multiple backup power supplies and determines whether the charge amount is lower than a predetermined charge amount, a backup power supply charging circuit that charges the backup power supply from the main power supply, where the backup power supply is determined by the backup power supply monitoring unit that the charge amount thereof is lower than the predetermined charge amount, and a power supply switching unit that switches to the backup power supply selected according to a predetermined rule if a voltage of the main power supply is reduced.

Abstract: A solid state imaging device having a light receiving region on a first surface side of a semiconductor substrate, incident light from an object to be imaged being illuminated on a second surface side of the semiconductor substrate, the solid state imaging device including an impurity diffusion layer formed on the first surface side of the semiconductor substrate, a surface of the impurity diffusion layer being silicided, and a gate electrode formed on the first surface side of the semiconductor substrate. The impurity diffusion layer includes the light receiving region disposed on the first surface side of the semiconductor substrate, a surface of the light receiving region being silicided, and the impurity diffusion layer includes at least a surface adjacent to the gate electrode.

Abstract: A control gate of a nonvolatile semiconductor storage device includes a first side surface on a side near a floating gate, a second side surface opposite to the first side surface, a silicide region formed in an upper portion of the control gate above the first side surface, and a protruding portion formed in an upper portion of the control gate above the second side surface. A side wall insulating film of the nonvolatile semiconductor storage device includes a first portion which covers at least a portion of the protruding portion without covering the silicide region, and a second portion which is provided continuously from the first portion and covers the second side surface with contacting the second side surface.

Abstract: A semiconductor device is provided with a first power supply cell, first cells and second cells. The first power supply cell and the first cells are continuously arrayed in a row direction in a first row. The second cells are continuously arrayed in the row direction in a second row adjacent to the first row. The first power supply cell is connected to a first power supply line extending perpendicularly to the row direction to feed a power supply voltage corresponding to a voltage fed from the first power supply line to the plurality of first and second cells. One of the second cells is indirectly connected to the first power supply line through the first power supply cell, the one of the second cells being positioned adjacent to the first power supply cell.

Abstract: A semiconductor device includes: a high VT part including a first transistor with first threshold voltage; a low VT part including a second transistor with second threshold voltage lower than the first voltage; a temperature detector which measures a temperature of the semiconductor device, determines whether the temperature is in a high temperature state where the temperature is higher than a predetermined temperature or a low temperature state where the temperature is lower than the predetermined temperature, and outputs a signal indicating the high temperature state or the low temperature state; and a controller which receives the signal indicating the high temperature state or the signal indicating the low temperature state, and performs control to cause the high VT part to operate based on the signal indicating the high temperature state and to cause the low VT part to operate based on the signal indicating the low temperature state.

Abstract: A network processor is connected to an external memory which includes storage areas for storing received data, and stores descriptors specifying locations of the storage areas, respectively.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.