Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is exposed to ionized air.

Abstract: A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an effective capacitance of the interconnect model to be inversely proportional to a voltage at the driving point node of the interconnect model; and storing the value of the effective capacitance. Such a method can be used to calculate effective capacitance of the interconnect model using analytical techniques.

Abstract: Reducing CMP wafer contamination by in-situ clean is disclosed herein. The invention can be employed in a method in which a conductive layer is formed on a surface of a semiconductor wafer. After a portion of the conductive layer is removed, an acidic solution is directly or indirectly applied to the semiconductor wafer. Then the semiconductor wafer is engaged with a polishing pad as the acidic solution is applied directly or indirectly to the semiconductor wafer. In one embodiment, the portion of the conductive layer is removed by a CMP tool, and the semiconductor wafer is engaged with the polishing pad before the semiconductor is removed from the CMP tool.

Abstract: An apparatus and method for monitoring pressure within an adhesion promotion unit is provided. The apparatus in one embodiment includes a chamber configured to receive and heat a semiconductor wafer. A vacuum device is in fluid communication with a processing space within the chamber, wherein the vacuum device is configured to create a vacuum within the processing space. A vacuum monitor is also in fluid communication with the processing space, wherein the vacuum monitor generates a first electrical signal if gas pressure within the processing space is below a predetermined value. The apparatus may further include a processor in data communication with the vacuum monitor and the vacuum device. The vacuum device may generate a second electrical signal, and the processor generates a third electrical signal if the vacuum monitor fails to generate the first electrical signal within a predetermined amount of time after the vacuum device generates the second signal.

Abstract: An apparatus for converting a PCI/PCI X device into a PCI-Express device. The apparatus may include a first circuit configured to receive first data, wherein the first circuit is configured to translate the first data into PCI formatted data. The apparatus may also include a PCI data bus and a second circuit coupled to the first circuit via the PCI data bus. The second circuit is configured to receive the PCI formatted data from the first circuit via the PCI data bus. The second circuit is configured to translate the PCI formatted data received from the first circuit into PCI-Express formatted data. However, the PCI data bus transmits data between only the first and second circuits.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is contacted with water for a period of time less than 120 minutes.

Abstract: In an active hybrid transformer circuit connected to both transmit and receive sides, a current driver is connected to a transmission path circuit through a common connection point of a load resistor and a replica resistor while a replica driver is connected to the replica resistor of which another connection point is directly connected to the receive side. The replica driver may be formed by a DAC of a current output type. A current ratio of the replica driver and the current driver is selected at a predetermined value so as to prevent a transmit signal from leaking into the receive side.

Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.

Abstract: A method involves: detecting a timing violation in a timing path included in an integrated circuit design; removing a wire, which couples two nodes in the integrated circuit design and is included in the timing path; and routing a new wire between the two nodes. The new wire is longer than the removed wire. The method can also involve: calculating timing information (e.g., delay and/or slew information) for the wires included in the timing path and selecting the wire for removal dependent on the timing information. In some embodiments, such a method eliminates timing violations that arise due to crosstalk in a single post-timing-analysis routing pass.

Abstract: Disclosed is an apparatus and method for flexible controlling endpoint memory within an USB device. In one embodiment, the method includes a USB device receiving a first token packet from a USB host, wherein the first token packet includes a first endpoint number. The first endpoint number is stored into a first tag in memory corresponding to a first data buffer in the USB device. The USB device then receives a data packet from the USB host, wherein the data packet comprises endpoint data. The; endpoint data of the data packet is stored into the first data buffer.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is exposed to ionized air.

Abstract: A de-interlacing architecture is taught. The de-interlacing architecture adopts a perceptual model to measure membership probabilities for a collection of image samples of an interlaced video source with respect to extracted static, motion, and texture image components of the same collection. The probabilities are used to prioritize contributions from the three image components and produce a progressive video sequence which is a summation of the portions of the aforementioned components. The perceptual model uses a dual-stage motion-based image difficulty measuring scheme to equalize contributions from the three image components in a manner that video artifacts in the output signal are least perceptive. A parameter mapping technique composed of several logic units, a decision function, a weight assignment block, and a look-up table, will be presented to derive the final component weights.

Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in a integrated circuit and forming electrically conductive interconnect lines after formation of the tungsten plugs, wherein at least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Separate from the formation of the tungsten plugs and electrically conductive interconnect lines, a gas is introduced into a liquid. At least one electrically conductive interconnect line is then contacted with the gas introduced liquid.

Abstract: A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an effective capacitance of the interconnect model to be inversely proportional to a voltage at the driving point node of the interconnect model; and storing the value of the effective capacitance. Such a method can be used to calculate effective capacitance of the interconnect model using analytical techniques.

Abstract: A method and apparatus relating to the safe handling of toxic gases are presented, including a gas fitting interlock apparatus comprising a pedestal portion; a fitting support portion disposed on the pedestal portion; an interlock nut clamp configured to be fastened to the fitting support portion; and a fastener for fastening the interlock nut clamp to the fitting support portion, the fastener being capable of being tightened to a tightness equal to or greater than a predetermined tightness sufficient to clamp a gas line disposed between the interlock nut clamp and the pedestal portion.

Abstract: An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder.

Abstract: A multidimensional equalizer and cross talk canceller for a communication network that simultaneously removes far end cross talk NEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A decision feedback equalizer determines a multidimensional steepest descent gradient to adjust matrix coefficients.

Abstract: A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. A vector is partitioned by the compiler into variable-sized streams which are transferred into and out of the processor as burst transactions. The compiler schedules transfers of vector streams required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers and each vector buffer is used at a specific time.