Abstract: The image processing apparatus includes an RGB-YUV converter for converting a color image into a luminance signal and a color difference signal and a YUV false color remover for removing false color based on the luminance signal Y and the color difference signals U, V. The false color remover includes an edge intensity calculator for calculating edge intensity based on the luminance signal Y, a modulation coefficient calculator for calculating a modulation coefficient so that a degree of modulation is greater as the edge intensity is higher, and a UV modulator for modulating a color difference signal having a value smaller than a prescribed threshold based on the degree of modulation.

Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.

Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.

Abstract: A laser diode has a plurality of structures, each of which having a function of scattering, absorbing or reflecting stray light, disposed in a region along an optical waveguide, wherein at least one of said structures is formed in each divided region obtained by equally dividing said region along said optical waveguide into three or more parts in the longitudinal direction of said optical waveguide.

Abstract: Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film (200) formed in a semiconductor layer, the element isolation film (200) defining an element formation region; a gate electrode (130) formed above the element formation region, the gate electrode (130) having ends respectively extending above the element isolation film (200); and impurity regions (110) which are to be a source region and a drain region which are formed in the element formation region so as to sandwich therebetween a channel formation region immediately under the gate electrode (130), the gate electrode (130) including at each of the ends thereof a high work function region (124) in which work function is higher than work function in other regions over at least a part of an interface between the element formation region and the element isolation film (200).

Abstract: A booster circuit includes first and second transistors, a first capacitor, a first drive circuit, a second capacitor, a first controller, and a second controller. The first and second transistors are connected in series between a first voltage and a second voltage. One end of the first capacitor is connected to a connection node between the first transistor and the second transistor. The first drive circuit boosts the voltage at the other end of the first capacitor. The second capacitor is connected between the second voltage and a reference voltage. The first controller controls conduction/non-conduction of the first transistor. The second controller inputs any of the first voltage and the second voltage to the second transistor, and thereby controls conduction/non-conduction of the second transistor. The boost circuit is supplied with the reference voltage, a supply voltage, and a boost clock signal, and generates the second voltage by boosting the supply voltage.

Abstract: A CCD image sensor includes: first and second CCD registers arranged so as to sandwich a pixel array therebetween, a first output portion provided to a connection part of the first and second CCD registers, a third CCD register which reads out and transfers the charge transferred by one of the first and second CCD registers, a second output portion provided to an end portion of the third CCD register, and a switch for changing whether or not to perform an output by the second output portion, depending on an operation mode.

Abstract: Provided is a liquid crystal display device including: an image signal line drive unit that supplies an image voltage depending on an output image to a plurality of image signal lines set in a matrix pattern on a liquid crystal panel constituted of a plurality of pixels; an offset direction detection unit that detects offset directions of offset voltages on the plurality of image signal lines; and an offset direction combination unit that collectively combines the offset directions of the offset voltages of the plurality of image signal lines into one direction based on the offset directions.

Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

Abstract: A display panel drive apparatus includes a source driver that drives each unit dot in accordance with a time-divisional clock, and a booster circuit that generates a supply voltage to be supplied to the source driver based on a clock having a rising edge and a falling edge each coinciding with an off-period of the time-divisional clock. The display panel drive apparatus performs a time-divisional driving operation during one horizontal period.

Abstract: Provided is a semiconductor device including a substrate, a gate insulating film which is formed on the substrate, and a gate electrode which is provided on the gate insulating film. The gate electrode includes a first metal silicide including a first metal material, and a second metal silicide including one of a second metal material and the second metal material in a contact portion between the gate insulating film and the gate electrode. The second metal silicide including the second metal material is a metal-rich silicide in which the composition ratio of the second metal material to silicon in the second metal silicide including the second metal is greater than 1.

Abstract: A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern.

Abstract: A data line driving circuit for a liquid crystal display device comprising: a plurality of first data lines applied with a positive potential, a plurality of second data lines applied with a negative potential, comparison units that compare with a reference voltage at least one of a potential at a first common line connected to the plurality of first data lines and a potential at a second common line connected to the plurality of second data lines, and switches that are controlled so that the first data lines and the second data lines are set to a connection state or an interruption state according to a comparison result by the comparison units.

Abstract: Provided is an insulated gate bipolar transistor (IGBT) which occupies a small area and in which a thermal breakdown is suppressed. The IGBT includes: an n-type semiconductor layer (3); and a collector part formed in a surface portion of the n-type semiconductor layer (3). The collector part includes: an n-type buffer region (14); and a p+-type collector region (15) and an n+-type contact region (18) which are formed in the n-type buffer region (14).

Abstract: A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed.

Abstract: Disclosed is a receiving device which comprises first and second AD converters for inputting a received analog signal and converting the analog signal to digital signals in response to sampling clock signals of mutually different phases, first and second adaptive equalizers for respectively receiving outputs of the first and second AD converters, third and fourth adaptive equalizers for respectively receiving outputs of the second and first AD converters, a first adder for adding the outputs of the first and second adaptive converters, a second adder for adding the outputs of the third and fourth adaptive equalizers, a first decision unit for receiving the output of the first adder, deciding a received symbol for output, and outputting a decision error, a second decision unit for receiving the output of the second adder, deciding a received symbol for output, and outputting a decision error, and a multiplexing circuit for multiplexing the received symbols output from the first and second decision units, for o

Abstract: In a semiconductor integrated circuit device including a charge pump circuit flowing an operating current therethrough, a current circuit is adapted to receive the operating current and a substantially constant current and generate an inverse current relative to the operating current and the substantially constant current.

Abstract: A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address on the first cell array with word lines corresponding to a specified row address on the second cell array.

Abstract: A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit.

Abstract: An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane. The lowermost vias are disposed so as to fit in a 4-row, 1-column rectangle, and the uppermost vias are disposed so as to fit in a 2-row, 2-column rectangle. The center of a via unit, which comprises the uppermost vias, as seen from the direction normal to the plane is disposed at the intersecting portion of the lowermost wiring layer and uppermost wiring layer. The center of a via unit, which comprises the lower vias, as seen from the direction normal to the plane is offset by a prescribed amount from the center of the via unit, which comprises the uppermost vias, as seen from the direction normal to the plane.