Abstract: Disclosed is a digital-to-analog converter in which a plurality of reference voltages that differ from one another are grouped into first to (S+1)th reference voltage groups. The digital-to-analog converter has a decoder and an amplifying circuit. The decoder includes: first to (S+1)th subdecoders for selecting respective ones of reference voltages corresponding to a value of a first bit group on an upper bit side of an input digital signal from the reference voltages of the first to (S+1)th reference voltage groups; and an (S+1)-input and 2-output type subdecoder for selecting and outputting two reference voltages out of reference voltages selected by the first to (S+1)th subdecoders, in accordance with a value of a second bit group on a lower side of the input digital signal.

Abstract: Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation circuit unit which generates a signal WEB which controls writing to and reading data from the semiconductor memory based on an scan FF value, and a test signal control circuit unit which controls the data address signal generation circuit unit and the WEB generation circuit unit, based on a received control signal, controls selectors, and selects and controls, as data and address signals to be supplied to the memory, data signal and address signals from the data address signal generation circuit unit or data and address signals via a user defined circuit.

Abstract: A display device disclosed herein prevents timing misalignment between signals of clock, data, and start pulses to be supplied to driver ICs. The display device comprises a controller, driver ICs and other components and each driver IC is configured to receive clock, data, and start pulses output from the controller, supply the received clock, data, and start pulses to a switch through parallel paths without routing the signals through its internal circuit, and supply the received clock, data, and start pulses to output terminals via the switch.