Abstract: In a circuit analyzing method, coordinate points of nodes in an analysis target circuit are detected from layout data of the analysis target circuit to store in a storage unit, and a minimum area from among areas is specified by referring to a storage unit to read out the coordinate points of the nodes and by defining the areas containing all the nodes based on the read coordinate points of the nodes. A distance parameter prescribing a size of the minimum area is calculated, a variation coefficient is specified by using the distance parameter. Thus, a delay time in the analysis target circuit is calculated by using the variation coefficient.

Abstract: An accelerated test for transistors included in inverter circuits of a semiconductor integrated circuit is to be improved in efficiency. Output terminals 30A, 30B of inverter circuits 11, 12, each including a CMOS circuit, may be short-circuited. A test circuit 20 supplies signals of mutually exclusive logical values to the inverter circuits 11, 12, whose output terminals 30A, 30B are in a short-circuited state. For testing, a switch 50 is turned on to short-circuit the output terminal 30A, 30B and signals of opposite logical levels are alternately supplied to the inverter circuits 11, 12 to cause the current to flow alternately through N-channel MOS transistors and P-channel MOS transistors included in the two CMOS circuits to activate the circuits.

Abstract: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %.

Abstract: A data transfer system includes a transceiver and a data processing apparatus coupled to the transceiver through a first line, a second line, and a third line. A data transfer method for the data transfer system includes, when data is transferred from the transceiver to the data processing apparatus, transmitting a first trigger signal from the data processing apparatus to the transceiver through the first line, transmitting a first clock signal from the transceiver to the data processing apparatus through the second line in response to the first trigger signal, and transmitting first transfer data from the transceiver to the data processing apparatus through the third line in synchronization with the first clock signal.

Abstract: A drive circuit of a liquid crystal display device according to the present invention applies drive potentials to common electrodes provided in common for a plurality of pixels of a liquid crystal panel. The drive circuit includes: a panel capacitance detection circuit, which detects the capacitance values of a liquid capacitor and a storage capacitor of the liquid crystal panel; and a drive potential adjustment circuit. In accordance with the capacitance values detected by the panel capacitance detection circuit, the drive potential adjustment circuit sets the drive potentials, which are to be applied to the common electrodes, to vary according to the detected capacitance values.

Abstract: A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

Abstract: A ring oscillator according to the present invention comprises: a ring oscillation unit, including a current starved inverter CSI having a current control P channel transistor P2, a signal transmission P channel transistor P3, a signal transmission N channel transistor N3 and a current control N channel transistor N2, and an in-phase signal transmitter receiving a signal from the current starved inverter, and outputting an in-phase signal to the current starved inverter; and a current control unit, including a basic current source having P channel transistor P10 and an N channel transistor N10 which is operated in a weak inversion state and flows a subthreshold current, and a current mirror circuit having a P channel transistor P12current-mirror connected to the P channel transistors P10 and P2, and an N channel transistor N12 current-mirror connected to the N channel transistor N2.