Abstract: A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.

Abstract: A basic logic element (1) includes: a calculation unit (11) configured to perform calculation processing; a self-diagnosis unit (12) configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit (13) configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit (12) and output a result of the determination as an authority signal; and an output control unit (14) configured to control whether or not to output the result of the calculation performed by the calculation unit (11) based on whether or not the authority to output data is retained by the management unit (13).

Abstract: To provide a technology in which a differential phase modulation manner can be applied to a space environment for satellite mounting, the optical receiver 10 includes a digital signal processing unit has: a level fluctuation frequency suppression unit 320 which suppresses a level fluctuation frequency component of the peak signal; an optical delay interference control unit 330 which generates an optical delay interference control signal, which is overdrive-amplified, on the basis of the peak signal of which the level fluctuation frequency component is suppressed and applies the generated optical delay interference control signal to the optical delay interferometer 210; and a data recovery unit 310 which recovers output data on the basis of the main signal from the wideband balanced optical detector 240.

Abstract: In order to provide processor elements and programmable devices, which have little restriction on logical block arrangement and wiring, and which can improve a degree of integration, processor element 1 includes: arithmetic units 11 that perform arithmetic processing on the basis of functions which have implemented instruction sets generated in accordance with programs; registers 12 that store arguments of the functions; bypass switches 13 of the arithmetic units 11; bypass switches 14 of the registers 12; a connection setting unit 16 that switches the connections of function units 20; a multiplexer 17 that switches the input to the connection setting unit 16; a demultiplexer 18 that switches the output destination of the output from the connection setting unit 16; and a selection unit 15 that switches, in accordance with a state, the bypass switches 13, 14, the connection setting unit 16, the multiplexer 17 and the demultiplexer 18.

Abstract: To provide a technology in which a differential phase modulation manner can be applied to a space environment for satellite mounting, the optical receiver 10 includes a digital signal processing unit has: a level fluctuation frequency suppression unit 320 which suppresses a level fluctuation frequency component of the peak signal; an optical delay interference control unit 330 which generates an optical delay interference control signal, which is overdrive-amplified, on the basis of the peak signal of which the level fluctuation frequency component is suppressed and applies the generated optical delay interference control signal to the optical delay interferometer 210; and a data recovery unit 310 which recovers output data on the basis of the main signal from the wideband balanced optical detector 240.

Abstract: Provided is a circuit structural body is formed into a shape including: A circuit structural body, including: a multilayer board, which includes a plurality of layers of a first to N-th tri-plate structural bodies each including a first to N-th (N is an integer of 2 or more) planar conductors; an interlayers connection conductor, which is configured to connect the first to N-th planar conductors to each other; and a side-surface ground conductor, which is formed on a side surface of the multilayer board, and is approximately parallel to and near the interlayers connection conductor.

Abstract: In order to provide processor elements and programmable devices, which have little restriction on logical block arrangement and wiring, and which can improve a degree of integration, processor element 1 includes: arithmetic units 11 that perform arithmetic processing on the basis of functions which have implemented instruction sets generated in accordance with programs; registers 12 that store arguments of the functions; bypass switches 13 of the arithmetic units 11; bypass switches 14 of the registers 12; a connection setting unit 16 that switches the connections of function units 20; a multiplexer 17 that switches the input to the connection setting unit 16; a demultiplexer 18 that switches the output destination of the output from the connection setting unit 16; and a selection unit 15 that switches, in accordance with a state, the bypass switches 13, 14, the connection setting unit 16, the multiplexer 17 and the demultiplexer 18.

Abstract: Provided is a circuit structural body is formed into a shape including: A circuit structural body, including: a multilayer board, which includes a plurality of layers of a first to N-th tri-plate structural bodies each including a first to N-th (N is an integer of 2 or more) planar conductors; an interlayers connection conductor, which is configured to connect the first to N-th planar conductors to each other; and a side-surface ground conductor, which is formed on a side surface of the multilayer board, and is approximately parallel to and near the interlayers connection conductor.

Abstract: An information record/reproduction apparatus includes logical volumes that can be used as a variable-length record/reproduction area and a physical volume that has been divided into a plurality of fixed-length areas and is not subjected to record or reproduction. Allocation to the logical volume is made by combining the divided fixed-length physical volumes by a management unit, and the size of the information storage area can be set depending upon, for example, a category of information to be recorded. If the amount of information of high priority exceeds a size of a predetermined logical volume corresponding to the information while no unused physical volume is available, then the management unit detaches part of a logical volume in which information of low priority has been recorded, allocates the detached part to the logical volume corresponding to the information, and thus records the exceeding amount of information.

Abstract: The present invention provides a dynamic circuit device that can prevent hardware and software from becoming larger in size and that can have smaller outside dimensions, less weight, and lower power consumption. For this purpose, the dynamic circuit device is provided with an operation instructing unit for instructing an operation and a cluster-layer wiring layer formed by disposing a plurality of cluster layers that include one or more lookup tables in which preset function elements are disposed and by connecting adjacent cluster layers with each other using cluster-layer connecting lines, wherein the dynamic circuit device changes the circuit configuration dynamically by changing operational states of the functional elements according to the instruction from the operation instructing unit.

Abstract: This automatic gain control circuit is provided with a variable gain amplifier for amplifying a received signal, has a small circuit size, and makes it possible to reduce the effect of superimposed external noise input within the frequency bandwidth of a received signal. The automatic gain control circuit supplies the output of the variable gain amplifier to an analog/digital converter and comprises: a frequency selection circuit that is connected to the output of the analog/digital converter and that selects a signal within the frequency bandwidth of a received signal, said signal having a narrower bandwidth than the frequency bandwidth; and a control signal generation circuit that generates a control signal for the variable gain amplifier on the basis of the strength of the signal selected by the frequency selection circuit.

Abstract: A package that hermetically seals an integrated circuit includes a metal lid (7) and a metal housing (10) having an open upper portion (12). In the package, the housing (10) includes in a wall surface thereof a glass unit (2) that seals a plurality of lead terminals therein. The glass unit (2) is disposed in a wall surface of the housing (10) such that a thickness in a vertical direction of the wall surface on an upper side of the glass unit (2) is determined according to a threshold limit value of a difference in temperature between glass that forms the glass unit (2) and metal that forms the wall surface.

Abstract: A deployable antenna reflector includes a surface cable network formed of a plurality of cables coupled to each other in a mesh pattern. The surface cable network includes at least one rigid rod member that reduces a maximum tensile force caused in the surface cable network.

Abstract: This automatic gain control circuit is provided with a variable gain amplifier for amplifying a received signal, has a small circuit size, and makes it possible to reduce the effect of superimposed external noise input within the frequency bandwidth of a received signal. The automatic gain control circuit supplies the output of the variable gain amplifier to an analog/digital converter and comprises: a frequency selection circuit that is connected to the output of the analog/digital converter and that selects a signal within the frequency bandwidth of a received signal, said signal having a narrower bandwidth than the frequency bandwidth; and a control signal generation circuit that generates a control signal for the variable gain amplifier on the basis of the strength of the signal selected by the frequency selection circuit.

Abstract: [Problem] Even if heat cycles are applied, degradation of joint strength is restrained. [Solution to problem] Lead solder joint structure, in which a first member is joined to a second member using lead solder, the structure comprising: a first solder layer that includes the first member as a core; a second solder layer that exists between the first solder layer and the second member and joins the first solder layer and the second member together; and a third solder layer that exists between the second solder layer and the second member.

Abstract: Provided is a temperature-compensated voltage divider circuit suppressing non-linearity of a divided voltage. A temperature-compensated voltage divider circuit includes a first voltage divider unit in which a plurality of diodes are connected in series, an one end thereof is an anode end, and the other end thereof is a cathode end, and a second voltage divider unit which is connected to the first voltage divider unit, the second voltage divider unit including a resister and a temperature compensator which are connected in parallel, the temperature compensator having a substantially linear temperature characteristic and suppressing temperature change of the resister.

Abstract: Provided is a redundant amplifier, including: a first switch for connecting, on a one-to-one basis, inputs P1 to Pm to m of outputs Q1 to Qn, where m and n are natural numbers and m<n is satisfied; a second switch for connecting, on a one-to-one basis, m of inputs R1 to Rn to m outputs S1 to Sm; and amplifiers A1 to An connected on a one-to-one basis between the outputs Q1 to Qn and the inputs R1 to Rn. Signal paths L1 to Lm are formed in accordance with a connection state between an input and an output of each of the first switch and the second switch, the signal paths L1 to Lm connecting the input P1 and the output S1, the input P2 and the output S2, . . . , and the input Pm and the output Sm, respectively, via any one of the amplifiers A1 to An. The connection state has at least two types in which the signal paths L1 to Lm each have the same length.

Abstract: Provided is an image capturing apparatus for capturing an image of a target object by optically scanning the target object by moving in a predetermined scanning direction. The apparatus includes a light-receiving device that is disposed on a light-receiving surface of the image capturing apparatus and accumulates an electric charge according to an amount of light received from a light detection window, a length of which in the scanning direction is shorter than a length in the scanning direction of an area defined as one pixel of the target object; and an output device that outputs the electric charge accumulated by the light-receiving device when the light-receiving device has completed the optical scanning of the area defined as one pixel.

Abstract: A radial line slot array antenna has a slotted conductor plate in which a plurality of slots are formed and arranged in a spiral. The plurality of slots are arranged in the slotted conductor plate such that the arrangement distance in a radial direction between the slots varies gradually between a first portion determined based on a first frequency and a second portion determined based on a second frequency that is different from the first frequency.