Patents Assigned to NEC Toppan Circuit Solutions, Inc.
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Patent number: 7317610Abstract: A sheet-shaped capacitor for storing electrical charges of large capacities, and to assure facilitated manufacture, cost reduction and improved reliability, and a method for manufacturing the capacitor. The capacitor includes a dielectric film 12, formed on a first major surface of a metal plate 11, an electrically conductive high polymer layer 13, formed on a first major surface of the dielectric film, and an electrically conductive layer 14 formed on a first major surface of the electrically conductive high polymer layer 13, such as by copper plating. A cathode electrode 20 is led out from the electrically conductive layer 14 on the side electrically conductive high polymer layer 13.Type: GrantFiled: November 15, 2005Date of Patent: January 8, 2008Assignees: NEC Toppan Circuit Solutions, Inc., NEC Tokin CorporationInventors: Hirofumi Nakamura, Yutaka Akimoto, Sadamu Toita, Takayuki Inoi, Katsuhiro Yoshida
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Patent number: 7303978Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.Type: GrantFiled: January 6, 2005Date of Patent: December 4, 2007Assignee: NEC Toppan Circuit Solutions, Inc.Inventor: Toshihide Ito
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Publication number: 20070241463Abstract: Metal posts are formed by etching a metal plate. Therefore, the metal posts can be formed with an accurate height and at a fine pitch. By connecting together upper and lower packages using the metal posts formed in the upper package, there is obtained a miniaturized semiconductor device having a fine electrode pitch.Type: ApplicationFiled: April 16, 2007Publication date: October 18, 2007Applicants: ELPIDA MEMORY, INC., NEC TOPPAN CIRCUIT SOLUTIONS, INC.Inventors: Masahiro Yamaguchi, Hirofumi Nakamura
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Patent number: 7106426Abstract: There is disclosed a method of inspecting an optical waveguide substrate for optical conduction at an increased inspecting rate and also inspecting an optical waveguide substrate for cross-talk. According to the disclosed method, a laser beam is applied from a laser beam scanning optical system to one end face of an optical waveguide of an optical waveguide substrate which is an object to be inspected, and the laser beam emitted from the other end of the optical waveguide is detected by a CCD camera, which output detected result data. A light spot position confirming device compares the detected result data with stored data.Type: GrantFiled: December 19, 2002Date of Patent: September 12, 2006Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada, Yoshio Matsumoto, Shinichi Tamabayashi
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Publication number: 20060120014Abstract: A sheet-shaped capacitor for storing electrical charges of large capacities, and to assure facilitated manufacture, cost reduction and improved reliability, and a method for manufacturing the capacitor. The capacitor includes a dielectric film 12, formed on a first major surface of a metal plate 11, an electrically conductive high polymer layer 13, formed on a first major surface of the dielectric film, and an electrically conductive layer 14 formed on a first major surface of the electrically conductive high polymer layer 13, such as by copper plating. A cathode electrode 20 is led out from the electrically conductive layer 14 on the side electrically conductive high polymer layer 13.Type: ApplicationFiled: November 15, 2005Publication date: June 8, 2006Applicants: NEC Toppan Circuit Solutions, INC., NEC Tokin CorporationInventors: Hirofumi Nakamura, Yutaka Akimoto, Sadamu Toita, Takayuki Inoi, Katsuhiro Yoshida
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Patent number: 6999643Abstract: After an optical waveguide substrate including a supporting substrate is adhered to an electric wiring board, the supporting substrate alone is dissolved using an organic solvent for removal. Alternatively, the supporting substrate alone is melted through a thermal treatment for removal. Further, a core layer of an optical waveguide is formed on the substrate using a photosensitive resin having a thermal expansion coefficient substantially identical to that of the supporting substrate.Type: GrantFiled: November 26, 2002Date of Patent: February 14, 2006Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada
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Patent number: 6938336Abstract: A resin filled board is manufactured by forming roughened surfaces on a conductive layer in a throughhole before it is filled with a resin, forming smooth surfaces on conductive layers on the top and bottom of the board, printing the resin using a mask having an opening at a position corresponding to the throughhole to selectively fill the resin in the throughhole, and curing the resin. In this way, the surface of the conductive layer around the throughhole is smoothed, so that hardly any of the resin remains on the surfaces near the throughhole when the surfaces of the board is mechanically polished after the resin is cured. Also, the filling resin will not fall down into the throughhole.Type: GrantFiled: October 18, 2002Date of Patent: September 6, 2005Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Toshihide Ito, Satoshi Nakamura
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Publication number: 20050156326Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.Type: ApplicationFiled: January 6, 2005Publication date: July 21, 2005Applicant: NEC Toppan Circuit Solutions, Inc.Inventor: Toshihide Ito
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Patent number: 6882544Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.Type: GrantFiled: June 25, 2003Date of Patent: April 19, 2005Assignees: NEC Toppan Circuit Solutions, Inc., NEC Tokin CorporationInventors: Hirofumi Nakamura, Satoshi Arai
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Publication number: 20040246690Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.Type: ApplicationFiled: June 25, 2003Publication date: December 9, 2004Applicants: NEC Toppan Circuit Solutions, Inc., NEC Tokin CorporationInventors: Hirofumi Nakamura, Satoshi Arai
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Patent number: 6791675Abstract: An optical waveguide path coupling structure is realized without requiring highly accurate alignment.Type: GrantFiled: November 29, 2001Date of Patent: September 14, 2004Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Kiminori Ishido
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Patent number: 6717494Abstract: Occurrence of EMI is reduced without a sharp increase of the manufacturing cost by suppressing a common mode current stably. There is provided a disclosed printed-circuit board being adapted such that a width of an outer edge section of a T-shaped pattern is widened so as to surround a recessed section with a frame-shaped additional electric conductor by electrically connecting the frame-shaped additional electric conductor with the T-shaped pattern making up a ground pattern so as to close the recessed section.Type: GrantFiled: March 20, 2002Date of Patent: April 6, 2004Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Toshiyuki Kaneko, Hideki Kikuchi, Kazuhiro Kinoshita, Kiyohiko Kaiya, Yutaka Akimoto
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Patent number: 6709803Abstract: After forming first catalyst cores on the surfaces of adhesive layers of an insulating substrate, a plating resist is patterned. The insulating substrate is treated with an aqueous solution containing an anionic surfactant. Then, the insulating substrate is soaked successively in a palladium—tin mixed colloid catalyst solution and an accelerator solution, whereby second catalyst cores are formed on the surface of the adhesive layer not covered with the plating resist. Thereafter, conductive circuits are formed by electroless copper plating. Due to the anionic surfactant, adsorption of the palladium—tin mixed colloid catalyst to the plating resist is suppressed, and the first catalyst cores promote the formation of second catalyst cores. By setting the concentration of the first catalyst cores to 4×10−8 atomic mol/cm2 or less, a fine conductive circuit with a line width/line space of 50 &mgr;m or less having a high electrical insulating property between circuit lines can be formed.Type: GrantFiled: February 20, 2002Date of Patent: March 23, 2004Assignee: NEC Toppan Circuit Solutions, Inc.Inventor: Sinichi Hotta
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Patent number: 6702176Abstract: A solder consists essentially of 1.0% to 4.0% of Ag by mass, 0.2% to 1.3% of Cu by mass, 0.02% to 0.06% of Co by mass, and the remaining of Sn and inevitable impurities.Type: GrantFiled: December 11, 2001Date of Patent: March 9, 2004Assignees: NEC Toppan Circuit Solutions, INC, Solder Coat Co., Ltd.Inventors: Toshihide Ito, Shiro Hara
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Publication number: 20030155638Abstract: To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads.Type: ApplicationFiled: January 24, 2003Publication date: August 21, 2003Applicant: NEC Toppan Circuit Solutions, Inc.Inventor: Toshihide Ito
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Patent number: 6608946Abstract: An optical module and its manufacturing method are provided which are capable of forming an optical waveguide by making the most of characteristics of a material having small optical transmission loss and excellent machinability or processibility. The optical module includes an optical waveguide sheet having a first optical waveguide and an optical component having a second optical waveguide, wherein the optical component is disposed in an aperture portion in the optical waveguide sheet and an end face of a large diameter portion of a core layer in the second optical waveguide is formed so as to be disposed opposite to an end face of a core layer of the first optical waveguide so that the first optical waveguide and the second optical waveguide are optically coupled.Type: GrantFiled: December 28, 2001Date of Patent: August 19, 2003Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Satoshi Nakamura, Mitsuo Saitou
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Publication number: 20030128907Abstract: After an optical waveguide substrate including a supporting substrate is adhered to an electric wiring board, the supporting substrate alone is dissolved using an organic solvent for removal. Alternatively, the supporting substrate alone is melted through a thermal treatment for removal. Further, a core layer of an optical waveguide is formed on the substrate using a photosensitive resin having a thermal expansion coefficient substantially identical to that of the supporting substrate.Type: ApplicationFiled: November 26, 2002Publication date: July 10, 2003Applicant: NEC TOPPAN CIRCUIT SOLUTION, INC.Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada
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Publication number: 20030117614Abstract: There is disclosed a method of inspecting an optical waveguide substrate for optical conduction at an increased inspecting rate and also inspecting an optical waveguid—e substrate for cross-talk. According to the disclosed method, a laser beam is applied from a laser beam scanning optical system to one end face of an optical waveguide of an optical waveguide substrate which is an object to be inspected, and the laser beam emitted from the other end of the optical waveguide is detected by a CCD camera, which output detected result data. A light spot position confirming device compares the detected result data with stored data.Type: ApplicationFiled: December 19, 2002Publication date: June 26, 2003Applicant: NEC Toppan Circuit Solutions, Inc.Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada, Yoshio Matsumoto, Shinichi Tamabayashi
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Publication number: 20030097311Abstract: An apparatus is disclosed for supporting acceptance of an order of a custom product. The apparatus is connected to a user terminal in a company through an Intranet and includes a price estimation unit, a price matching unit, a storage unit and a WWW server. The apparatus first provides, to a user having a user registration, a menu of functions which can be utilized based on a division of the user in response to an access from the user terminal. When the WWW server receives a price estimation request for a custom product including product specifications and negotiation information from the user terminal, the price estimation unit calculates an estimated price. When the price matching unit receives a price matching request from the price estimation unit, it transmits an e-mail to the terminal of a person who perform the price matching to urge the person to issue an answer to the price matching. Necessary data including specification matching of the past are registered in the storage unit.Type: ApplicationFiled: November 18, 2002Publication date: May 22, 2003Applicant: NEC Toppan Circuit Solutions, Inc.Inventors: Noriko Shinohara, Kimio Iwasawa
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Patent number: 6563057Abstract: In a multilayer printed circuit board having a conductor pattern, covered with an insulation layer having via holes, these via holes are filled with a conductor by means of electroless nickel plating or electroless copper plating.Type: GrantFiled: February 9, 2000Date of Patent: May 13, 2003Assignee: NEC Toppan Circuit Solutions, Inc.Inventors: Sinichi Hotta, Hisaya Takahashi