Abstract: Microalgae cultivation equipment for the cultivation of microalgae is provided in which a raceway is modified so as to contain multiple generally upright photobioreactor columns spaced apart along its length so as to increase the total surface area of liquid growth medium directly exposed to light and to improve the transfer of CO2 from the gas-phase to the liquid-phase by providing adequate height inside the vertical photobioreactor columns. The lowermost ends of the photobioreactor columns are immersed inside the liquid growth medium in the raceway component and are fed with liquid growth medium by a circulation promoting facility circulating the liquid growth medium from the raceway through the photobioreactor columns to become discharged back into the raceway. Gas inlets provide CO2 containing gas bubbles passing upwards in each of the photobioreactor columns. One or more paddle wheels or jet pumps induce a flow of liquid growth medium within the raceway.

Abstract: A multistep continuous flow synthesis method for the manufacture of isonicotinyl-hydrazide (Isoniazid) comprising reacting 4-cyano pyridine with NaOH at a specified molar ratio and temperature range to produce the intermediate isonicotinamide, which intermediate is reacted with hydrazine hydrate, without isolation thereof, at a specified molar ratio and temperature range to produce isonicotinyl-hydrazide (Isoniazid) in a yield greater than about 90%.

Abstract: This invention provides for a flow synthesis process for producing Oseltamivir and pharmaceutically acceptable salts thereof from shikimic acid in particular but not exclusively to a flow synthesis process for producing Oseltamivir phosphate from shikimic acid in a nine-step flow synthesis that provides for superior reaction times and product yields compared to known methods.

Abstract: A circuit structure and a method for supressing single event transients (SETs) or glitches in digital electronic circuits are provided. The circuit includes a first input which receives an output of a digital electronic circuit and a second input which receives a redundant or duplicated output of the digital electronic circuit. The circuit includes only four two-input gates of two different kinds selected from AND, OR, NAND and NOR gates. The four two-input gates being arranged so that a final circuit output is impervious to a change in a logic level of only the first input or only the second input, and the final circuit output is equivalent to the logic level of the first and second inputs when the logic level of the first and second inputs match.