Abstract: A method for processing a variable length code comprising: determining a first address; decoding opcodes from the at least one table starting at a first address; in response to each of the opcodes: receiving a portion of a sequence of bits, the sequence of bits comprising a first variable length code; receiving S from the second table at the current address; flushing S bits in the sequence of bits; receiving T corresponding to one of the stages; determining a value of a set of T bits in the sequence of bits; receiving D from the second table at the current address; and computing the next address, the next address being the sum of the current address, D, and the value of the set of T bits; and retrieving the next opcode, the next opcode being retrieved from the next address; and determining the decoded syntax element.

Abstract: A data processing method with multiple issue multiple datapath architecture in a video signal processor (VSP) is provided. In the method, commands are received from the external signal processor. The received commands are routed to a plurality of separate command sequencers, an Input/output (IO) processor or a plurality of configure registers according to different command types. Each of the separate command sequencers packs the received commands into a plurality of instruction packets and sending the instruction packets to a plurality of instruction dispatch units, in which each of the instruction packets includes one or more instructions. The instruction packets are dispatched to respective function units for performing operations in response to the received instruction packets.

Abstract: A method for processing a variable length code comprising: determining a first address; decoding opcodes from the at least one table starting at a first address; in response to each of the opcodes: receiving a portion of a sequence of bits, the sequence of bits comprising a first variable length code; receiving S from the second table at the current address; flushing S bits in the sequence of bits; receiving T corresponding to one of the stages; determining a value of a set of T bits in the sequence of bits; receiving D from the second table at the current address; and computing the next address, the next address being the sum of the current address, D, and the value of the set of T bits; and retrieving the next opcode, the next opcode being retrieved from the next address; and determining the decoded syntax element.