Abstract: A high-voltage switching device for a flash memory includes at least one pumping transistor which includes one junction terminal and another junction terminal which are commonly connected to a control signal, and a gate terminal connected to a select signal. The high-voltage switching device also includes at least one switching transistor that includes one junction terminal connected to an input signal, another junction terminal connected to an output signal, and a gate terminal connected to the select signal. A layout of the high-voltage switching device includes a pumping active area in which the one junction terminal and the another junction terminal of the pumping transistor are disposed; a control interconnection area in which an interconnection of the control signal is wired; and a select interconnection area in which an interconnection of the select signal is wired.

Abstract: A flash memory device reduces noise peak and program time through serial programming of program blocks of memory cells. The time interval or the number of the program groups is decreased according to the proceeding program loop in the plurality of program loops, reducing the total program time.

Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.

Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.