Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.

Abstract: Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory includes setting programming conditions on word lines to set up programming of multiple memory cells associated with multiple bit lines, and sequentially enabling bit line select gates to load data from a page buffer to the multiple bit lines of the memory. After each bit line is loaded with selected data, an associated bit line select gate is disabled so that the selected data is maintained on the bit line using bit line capacitance. The method also includes waiting for a programming interval to complete after all the bit lines are loaded with data to program the multiple memory cells associated with the multiple bit lines. At least a portion of the multiple memory cells are programmed simultaneously.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a drain P+ diffusion deposited in the N-well, a source P+ diffusion deposited in the N-well, and an oxide layer deposited on the N-well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: A method of storing information or data in a nonvolatile memory device with multiple-page programming. The method, in one aspect, is able to activate a first drain select gate (“DSG”) signal. After loading the first data from a bit line (“BL”) to a nonvolatile memory page of a first memory block in response to activation of the first DSG signal during a first clock cycle, the first DSG signal is deactivated. Upon activating a second DSG signal, the second data is loaded from the BL to a nonvolatile memory page of a second memory block. The first data and the second data are simultaneously written to the first memory block and the second memory block, respectively.

Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

Abstract: A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N-well, an oxide layer deposited on the N-well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

Abstract: A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: A memory system is configured to store information using a hybrid volatile and nonvolatile memory device. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.

Abstract: A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.

Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract: A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.

Abstract: A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.

Abstract: A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90 nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90 nm in length.