Abstract: Associative processing methods and apparatus are described for processing graphics data for three-dimensional graphic displays, e.g., in three-dimensional games. A texture, which comprises a bitmap image used to apply a design onto the surface of a 3D computer model for 3D graphics display, may be converted to APA (associative processor apparatus) instructions.

Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.

Abstract: A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Abstract: Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the carry bit of each loop iteration is carried forward to the next loop iteration. At most five logical operations are used per loop iteration for addition, and at most seven logical operations, of which at most five are binary logical operations, are used per loop iteration for subtraction. In each loop iteration, the second input bit is a direct or indirect argument of at most three logical operations in addition, and of at most four logical operations in subtraction. Each loop iteration includes at least one OR operation and at most two XOR operations.

Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: A method of performing in-place arithmetic, particularly addition and subtraction, on numbers stored in respective consecutive rows of an array processor that has two tags registers. In a first machine cycle per bit, results of logical operations are stored in the tags registers, and the tags registers are shifted to align the intermediate results with other rows. In a second machine cycle per bit, results of further logical operations are stored in the tags registers, and the tags registers are shifted back to align the new intermediate results with the original rows.

Abstract: Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the carry bit of each loop iteration is carried forward to the next loop iteration. At most five logical operations are used per loop iteration for addition, and at most seven logical operations, of which at most five are binary logical operations, are used per loop iteration for subtraction. In each loop iteration, the second input bit is a direct or indirect argument of at most three logical operations in addition, and of at most four logical operations in subtraction. Each loop iteration includes at least one OR operation and at most two XOR operations.

Abstract: An Internet imaging device, such as camera, scanner and digital television display, is disclosed. The device combines the advantages of platform-independent page description languages, such as Adobe PostScript 3, with an imaging device that connects directly to remote locations via the Internet. The device outputs image data and image processing commands in a platform-independent page description language via cordless communication such as a cellular phone. The data are transferred directly to remote display units, such as printers and digital televisions, thereby eliminating two personal computers (PCs): one at the input end of the communication and one at the output end. The device taught by the present invention need not include a flash memory or other storage medium, as images are transferred directly when generated.

Abstract: A data processing device includes an associative processor that in turn includes an array of content addressable memory (CAM) cells and a plurality of tags registers. The device also includes a memory for storing the data and a bus for exchanging the data with the associative processor. Data are exchanged in parallel, via one of the CAM cell columns, one column of data at a time.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare o

Abstract: A data processing device includes an associative processor that in turn includes one or more arrays of content addressable memory (CAM) cells and two or more tags registers. The device also includes a memory for storing the data and a bus for exchanging the data with the associative processor. During input and output operations, data are exchanged in parallel, via one of the tags registers. Another tags register is used to select rows of CAM cells for input or output. By appropriately shifting the bits in the buffer tags register between write or compare operation cycles, entire words are exchanged between the selected CAM cell rows and the buffer tags register. During arithmetical operations, in an embodiment with multiple CAM cell arrays, different tags registers are associated with different CAM cell arrays at will.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare op

Abstract: A method and apparatus is disclosed for a fast, one-dimensional, discrete cosine transform (1D DCT) of eight samples, and for a fast, one-dimensional, inverse discrete cosine transform (1D IDCT) for eight coefficients, requiring five parallel additions, five parallel subtractions and one parallel multiply operation. According to one embodiment, the parallel additions and subtractions are executed by performing a parallel add/subtract operation. The data are manipulated in a processor operable to execute add, subtract and multiply operations on a plurality of pairs of data values in parallel. According to a preferred embodiment of the invention, this processor is an associative memory array, typically consisting of several thousands of memory words. The inherent scalability of the associative memory enables increasing throughput by simply increasing the size of the associative memory, enabling performing the 1D DCT for large numbers of samples.